Hold Mode Research Articles

Controller design and remote piloting training module development for unmanned cropped delta reflex wing configuration

In this study, a cost-effective high-fidelity six-degree of freedom module augmented with an onboard controller is developed. The unmanned aerial vehicle (UAV) under consideration is a wing-alone configuration with a cropped delta planform and reflex airfoil cross-section designed to perform manoeuvres at high angles of attack. The six-degree of freedom dynamics for the aforementioned configuration is developed based on Newtonian mechanics incorporating linear and nonlinear aerodynamic models to expand flight simulations in corresponding regimes. Aerodynamic stability and control parameters for the simulations are obtained from full-scale wind tunnel measurements and flight tests. It is observed that the linear aerodynamic model is valid in angle of attack (α) domain −5°≤α≤10°, followed by nonlinearity up to α≈21°, post which lift coefficient remains almost constant with angle of attack till 45°. The simulation model is validated with the corresponding flight data obtained from flight tests. A user-friendly graphical interface with real-time animation of UAV has been developed for the aforementioned configuration by integrating MATLAB and Flightgear environment with real-time control input from the hardware to enable the pilot for visual and tactile feedback, respectively. A controller based on total energy control is designed for velocity and altitude hold modes, while an attitude hold controller is designed for pitch and roll angle tracking to enable controller-in-the-loop remote piloting simulations. In order to enhance practical applicability, the designed module has been tested under various simulated wind conditions. It is noticed from the results that the steady-state error in attitude remains below 2% with a maximum overshoot of 5° from reference. The total energy controller achieves a zero steady-state error with a maximum overshoot of 2 m/s for velocity and 6 m for altitude, respectively. The developed module enhances remote piloting training, flight response assessment, and control algorithm testing for cropped delta planform UAVs.

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Many scientists are working to develop a static random-access memory (SRAM) cell that used little power and has good stability and speed. This work introduces a fin field effect transistor developed SRAM cell with 10 transistors (10T FinFET SRAM). A cross connected standard inverter and schmitt-trigger inverter is used in the proposed 10T FinFET SRAM cell. We introduce the schmitt trigger based SRAM cell with single-ended read decoupled and feedback-cutting approaches to enhance the static noise margin (SNM) and access time of the SRAM cell. The proposed cell’s power utilization is decreased with the help of stacked N-FinFETs. For determining the relative performance of the proposed 10T FinFET SRAM cell design in terms of fundamental design metrics, it has also been compared with some of the current SRAM cells, including 6T, SBL9T SRAM, 10T SRAM, and DS10T SRAM. The simulation results at 0.6V demonstrate that the suggested design achieves low power utilization when Reading, writing and hold modes of operation in comparison to the aforementioned bit cells. It maintains a high SNM during all operations. The suggested cell is the one with fastest read access. The simulation is carried out with cadence tool using FinFET 18 nm technology.

Design and Simulation of a Novel 16T SRAM Cell for Low Power Memory Architecture

Static random access memory (SRAM) is a sort of RAM where information is not permanently stored and does not require routine updating. To reduce leakage power without sacrificing performance, a variety of approaches have been applied to SRAM cells. In this study, we suggest a new 16T SRAM design that can function in active, park, standby, or hold modes. A fully static mode of operation for SRAM is made possible by the 16T SRAM structure, which also enhances write margin (WM) and removes charging conflict between devices during read and write operations. The key objectives of the suggested architecture are to retain logic state in park mode while maintaining stability and reducing standby time in active mode, as well as to reduce leakage current in standby mode. This is done by removing feedback from the back-to-back inverters during write operations via the data-dependent supply block. This makes it possible for the suggested bitcell to considerably increase the WM. A novel SRAM cell with 16 transistors is created with subthreshold operation and enhanced data stability. By using an equalized bit line technique to avoid leakage due to enhanced data pattern and RBL detection, the suggested single-ended SRAM cell with dynamic feedback control lowers the static noise margin for ultra-low power transfer. A sleep transistor is incorporated into the architecture to save power consumption when the system is in standby mode due to inefficient voltage transmission. Tanner EDA tool V.14.1 on 45-nm CMOS was used for design and simulation. The outcomes demonstrate a considerable decrease in no-load current and power loss.

High-Stability and High-Speed 11T CNTFET SRAM Cell for MIMO Applications

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput. 30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.

A Single-Ended 9T SRAM Cell With Improved Noise Margin for Low-Power Applications Used in LEDoS

As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is a significant barrier to approaching the higher performance of microdisplay. In this paper, a new low-power SRAM cell with a single bitline is proposed to reduce the power dissipation of digital CMOS drivers. Compared with conventional differential 6T SRAM cell, the proposed 9T uses the single-ended read/write and read/write separation technology by reducing bitline and adding word lines, and write/read static noise margin (WSNM/RSNM) has been improved while the power dissipation is reduced effectively by stacking effect. When VDD is 0.8 V, the proposed cell achieves 1.4× and 2.2× improvement in WSNM and RSNM compared to D6T. Besides, the proposed cell consumes 1.4× less power during hold mode compared to D6T at VDD=0.8 V.

Ultra-low leakage static random access memory design

An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropriate for hold mode applications. The simulations are carried out by using Cadence (Virtuoso Schematic and layout editor) tools with GPDK45-nm technology.

Radiation-hardened flip-flop for single event upset tolerance

PurposeThe purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).Design/methodology/approachWith SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.FindingsSimulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.Originality/valueIn this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.

Hover Handling Qualities of Fixed-Pitch, Variable-RPM Quadcopters of Increasing Size

Fixed-pitch, variable-RPM quadcopters of increasing size are simulated in hover. Three aircraft sizes are considered, with rotor diameters of 4, 6, and 8 ft(1.2, 1.8, and 2.4 m) and gross weights of 300, 680, and 1200 lb (136, 308, and 544 kg) respectively. Control design is performed for each aircraft using CONDUITR, first using standard ADS-33E-PRF handling qualities specifications. Froude scaling is then applied to the specifications in order to design more comparable, aggressive controllers for the two smaller aircraft. Piloted commands and gust inputs are simulated in the time domain in order to estimate the necessary motor current margins needed for adequate maneuverability local to hover. Of the maneuvers considered, a yaw rate step requires the highest current margin for the smallest aircraft, while the longitudinal velocity step requires the highest current margin for the others, regardless of the Froude scaling of the handling qualities metrics. Using the maximum current values from these simulations, the motor weight fraction is 8.3–10.6% for the 300-lb vehicle, 11.6–13.0% for the 680-lb vehicle, and 15.8% for the 1200 lb. Motor weight requirements can be reduced on the larger two aircraft by flying with the pitch and roll axes exclusively in the attitude command, attitude hold mode, rather than translational rate command. In this case, step commands in yaw rate are limiting for the 680-lb vehicle (10.7–11.8% motor weight fraction) and heave commands are limiting for the 1200-lb vehicle (13.6% motor weight fraction). Estimated motor weight requirements are also reduced by decreasing the rotor inertia and introducing additional filtering into the aircraft commands.

Practical Control for Multicopters to Avoid Non-Cooperative Moving Obstacles

Unmanned Aerial Vehicles (UAVs) are now becoming increasingly accessible to amateur and commercial users alike. The main task for UAVs is to keep a prescribed separation with obstacles in the air. In this paper, a collision-avoidance control method for non-cooperative moving obstacles is proposed for a multicopter with the altitude hold mode by using a Lyapunov-like barrier function. Lyapunov-like functions are designed elaborately, based on which formal analysis and proofs of the proposed control are made to show that the collision-avoidance control problem can be solved if the moving obstacle is slower than the multicopter. The result can be extended to some cases of multiple obstacles. What is more, by the proposed control, a multicopter can keep away from obstacles as soon as possible, once obstacles enter into the safety area of the multicopter accidentally, and converge to the waypoint. Simulations and experiments are given to show the effectiveness of the proposed method by showing the distance between UAV and waypoint, obstacles respectively.

Evaluation of the Integrity Risk for Precise Point Positioning

Global Navigation Satellite System (GNSS) Precise Point Positioning (PPP) is an attractive positioning technology due to its high precision and flexibility. However, the vulnerability of PPP brings a safety risk to its application in the field of life safety, which must be evaluated quantitatively to provide integrity for PPP users. Generally, PPP solutions are processed recursively based on the extended Kalman filter (EKF) estimator, utilizing both the previous and current measurements. Therefore, the integrity risk should be qualified considering the effects of all the potential observation faults in history. However, this will cause the calculation load to explode over time, which is impractical for long-time missions. This study used the innovations in a time window to detect the faults in the measurements, quantifying the integrity risk by traversing the fault modes in the window to maintain a stable computation cost. A non-zero bias was conservatively introduced to encapsulate the effect of the faults before the window. Coping with the multiple simultaneous faults, the worst-case integrity risk was calculated to overbound the real risk in the multiple fault modes. In order to verify the proposed method, simulation and experimental tests were carried out in this study. The results showed that the fixed and hold mode adopted for ambiguity resolution is critical to an integrity risk evaluation, which can improve the observation redundancy and remove the influence of the biased predicted ambiguities on the integrity risk. Increasing the length of the window can weaken the impact of the conservative assumption on the integrity risk due to the smoothing effect of the EKF estimator. In addition, improving the accuracy of observations can also reduce the integrity risk, which indicates that establishing a refined PPP random model can improve the integrity performance.

A 25-GSa/s InP DHBT Track-and-Hold Amplifier Using Active Peaking Input Buffer

In this letter, we present a 25-GSa/s wideband track-and-hold amplifier using 0.8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> indium phosphide (InP) process for high-speed analog sampling front-end. In this design, an active peaking input buffer is first used in the base–collector switching diode sampler. Moreover, it is carefully calculated and analyzed. The dominant pole in the signal path of the circuit is canceled by one zero produced by the active peaking structure; therefore, the bandwidth (BW) is extended. The experimental results show that a total harmonic distortion (THD) of less than −27 dBc and a spurious-free dynamic range (SFDR) of better than 32.5 dB are demonstrated at a 25-GSa/s sampling rate. In the hold mode, the isolation is better than −42 dB. In addition, it has an 0.156 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f_{T}}$ </tex-math></inline-formula> BW from dc to 25 GHz within 160-GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f_{T}}$ </tex-math></inline-formula> , which is a very competitive value compared with other reported track-and-hold amplifiers (THAs) using the InP process.

A novel PVT‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub‐threshold region

AbstractThis paper presents a process voltage temperature (PVT)‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell at 32 nm. The cell uses a modified Schmitt‐trigger action in all operating modes for performance improvement, a characteristic that is not exhibited by existing SRAM cells. The action improves the stability of stored data in read and hold modes and assists the write process to enable a faster and low‐voltage write operation. Additionally, the cell uses negative bitline technique and fully‐gated grounded scheme for achieving further improvement in write ability and ION/IOFF ratio. The proposed cell shows 34.9% reduced deviation in switching threshold voltage in comparison to conventional structure. Further, improvement of up to 211% in write ability and 169% in ION/IOFF ratio is obtained over existing SRAM cells operating in sub‐threshold region. The cell takes up to 86% and 99% lesser read and write access time, respectively. The Monte‐Carlo simulations show the robust performance of proposed cell. The cell has reduced write, read, and hold failure probabilities resulting in overall Vmin of 425 mV, which is the least among the cells considered for comparison, thus making it an amenable design suitable for sub‐threshold operation under PVT‐variations.

A 32 nm single-ended single-port 7T static random access memory for low power utilization

In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV. The static noise margin for the read and hold modes is 90 mV, while the write margin is 180 mV. Monte Carlo analysis for 6σ global variations and temperature variation analysis for temperatures in the range −10 °C to 80 °C validate its performance. The cell is compared with other single-ended 5T, 6T, 7T, 8T, 9T and 10T SRAM cells and is found to be superior in performance. As the leakage current is low, the I ON /I OFF ratio is high compared with the other cells. The power consumption of the bit cell is also found to be minimal for all modes of operation. The dynamic write analysis demonstrates that the proposed cell completes the write operation in a 10 ns pulse width. Moreover, the improvement in performance is obtained for an area as low as 0.539 µm2. The area of 5T, 6T, 7T-1, 7T-2, 7T-4, 7T-5, 8T, 9T and 10T cells is greater than the 7TP bit cell area by 22.17%, 51.8%, 35.8%, 13.9%, 30.4%, 6.78%, 56.6%, 63.3% and 75.5%, respectively.

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

AbstractGraphene nanoribbon and transition metal dichalcogenide field‐effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal‐oxide‐semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single‐ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95×/3.20× and incurs a penalty of 1.16×/1.14× in read delay compared to the GNRFETs/TMDFET‐based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross‐coupled inverters pair during the write operation, enhancing write static noise margin by 1.65×/1.71×. These two TGs along with high logic level of virtual ground (VGND) control signal during hold mode reduce leakage power. Existence of a higher number of p‐type MOS (PMOS) devices, the presence of stacked transistors, and being single‐ended bitcell further reduce this metric, nearly 1.48×/1.17× designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET‐based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half‐select disturb, and therefore, bit‐interleaving architecture can be applied to reduce multi‐bit errors.

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

The Impact of Icing on the Airfoil on the Lift-Drag Characteristics and Maneuverability Characteristics

Icing has now become an important factor endangering flight safety. This paper takes the icing data of the NACA 23012 airfoil as an example, establishes an icing influence model for real-time simulation based on icing time and aircraft angle of attack, and analyzes the influence of different icing geometry on aircraft characteristics. The two-dimensional interpolation method is used to improve the model of the aircraft’s stall area, which is mainly divided into the correction of the lift-drag coefficient linear area and the stall area and the correction of the aircraft stability derivative and the control derivative. The aerodynamic equation of the airplane after icing is established, and the modal analysis of the airplane under different icing conditions is completed through the linearization of the flight equation. The closed-loop simulation system of the altitude holding mode and roll attitude holding mode is used to calculate and analyze the flight quality changes of the aircraft after the wing surface is frozen. The analysis results show that, under icing conditions, in the range of small angles of attack, icing has no obvious influence on the aircraft mode. As the degree of icing increases, the throttle skewness and the negative deflection angle of the airplane’s level flight requirements continue to increase. The case of icing flight in altitude hold and roll hold modes shows that flying in the autopilot mode under severe icing conditions is very dangerous and is prone to cause the aircraft to stall.

Design and Analysis of SRAM cell using Body Bias Controller for Low Power Applications

Low power consumption of electronic devices has become one of the most desirable factors in the present day’s technology. Static random access memory (SRAM) being an integral part of most of the electronic gadget suffers from leakage current which results in static power dissipation and subsequently affects its performance particularly during standby or hold mode. This becomes crucial especially for those systems which are portable and have limited power supply. This work therefore proposes a body bias controller implemented with a 7T SRAM cell at 28 nm CMOS technology node which lowers the static power consumption and increases the hold static noise margin (HSNM) of SRAM during standby mode by changing the threshold voltage. Moreover, it also reduces write delay due to reduction in threshold voltage of proposed design without having a significant effect on write static noise margin and read static noise margin. It has been noticed that there is a reduction of 40%, 28%, 41.9% and 30% in static power dissipation whereas there is an enhancement of 19%, 14.2%, 6.6% and 5.2% in HSNM of the proposed design when compared to 6T SRAM cell, 7T SRAM cell, WRE8T SRAM cell and 9T SRAM cell, respectively. The proposed design can thus be a suitable alternative for low power SRAMs.

Balanced sampling switch for high linearity and a wide temperature range in low power SAR ADCs

This Letter proposes a balanced sampling switch technique for achieving high linearity and a wide temperature range. The proposed technique reduces the V DS of the NMOS sampling switch for reducing the leakage current through the switch during the hold mode. This operation is implemented by a mini capacitive digital-to-analogue converter (C-DAC) that mimics the main C-DAC used for main SAR conversion. The proposed sampling switch is applied to a 10-bit, 0.5 V SAR ADC with 5 Msample/s and verified by comprehensive simulation. Compared to the conventional sampling switch without the mini C-DAC, the proposed switch improves SFDR and SNDR by 27.52 dBc and 11.8 dB, respectively, at the FF corner and 120°C.

Piezoelectric response of hydrated HAp-based materials containing different calcium concentrations

Piezoelectric signals were obtained from hydroxyapatite disks with different concentrations of calcium ions when they were subjected to different compression stresses. The samples were hydrated by immersing in water during 15 s and placed between electrodes in order to compress them using a mechanical test machine; the maximum applied stress was of 35.5 MPa. Two different compression modes were used: a) hold mode: once the maximum load was reached, it was kept applied to the sample during 5 min, and b) release mode: the maximum load was removed rapidly while the electrical signal was recorded during 5 min. In all cases the piezoelectric voltages reduces exponentially to zero with different characteristic times and voltage amplitudes, depending on the compression mode and the calcium concentration. The samples were also characterized using: X-Ray Diffraction, Dielectric Relaxation Spectroscopy and mechanical test.

High Stable and Low Power 8T CNTFET SRAM Cell

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [Formula: see text], [Formula: see text]) and Dual chiral value (NCNTFET with [Formula: see text], [Formula: see text] and PCNTFET [Formula: see text], [Formula: see text]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.