Hold Mode Research Articles

A 1.2- mu m BiCMOS sample-and-hold circuit with a constant-impedance, slew-enhanced sampling gate

A new sampling gate circuit, with dual outputs functioning alternately in the track and hold modes, is integrated in an open-loop sample-and-hold circuit architecture achieving greater than 450-MHz small-signal input bandwidth and 100-MHz maximum sample rate. The sampling gate also incorporates slew enhancement techniques to achieve (+430 V/ mu s, -510 V/ mu s) slew rate and features a 'built-in' buffer to maintain constant input impedance for both the track and hold modes, simplifying design of the front-end input buffer. Special on-chip clock generation circuits are used to minimize sampled pedestal (+4 mV). Power dissipation is less than 300 mW, including output driver. Measured harmonics are 58 dB down for a 2 V/sub p-p/ 20-MHz sine wave sampled at 100 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Current-mode CMOS latched quaternary threshold logic full adder

A current-mode CMOS circuit that realises the latched quaternary threshold logic full adder function has been realised in standard polysilicon-gate CMOS technology. In its FOLLOW mode, the quaternary full adder accepts two quaternary inputs and a binary CARRY input and develops a two-quaternary-digit output word that is the base-four sum of the inputs. In the HOLD mode, these output states are held by a eight-valued current-mode latch subcircuit. A current-mode CMOS latched quaternary threshold logic full adder circuit is presented and experimental performance described.

A high-speed sample-and-hold technique using a Miller hold capacitance

A circuit technique is introduced for increasing the precision of an open-loop sample-and-hold circuit without significantly reducing the sampling speed. With this technique, the sampling error resulting from input-dependent charge injection of the sampling switch is significantly attenuated by sampling the input voltage onto a capacitance that is small during the sample mode but is, in effect, increased during the transition to the hold mode through the action of Miller feedback. The technique thus allows for a high sampling speed without the precision penalty traditionally associated with open-loop sample-and-hold circuits. A sample-and-hold circuit based on the proposed approach has been designed and fabricated in a 1- mu m CMOS technology, and an order-of-magnitude of reduction in the input-dependent charge injection has been demonstrated experimentally. This prototype circuit is capable of sampling an input to a precision of 8 b with an acquisition time of 5 ns. The experimental sample-and-hold circuit operates from a single 5-V supply and dissipates 26.5 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

4932028 Error log system for self-testing in very large scale integrated circuit (VLSI) units

A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.

A high-speed current-multiplexed sample-and-hold amplifier with low hold step

A monolithic high-speed sample-and-hold amplifier is described. It minimizes the hold step via a new circuit architecture. This design takes advantage of the speed of open-loop sample-and-hold circuits during the sample mode and cancellation of charge injection by duplicating and feeding it through a second amplifier during the hold mode. The unique feature of the design is an acquisition time of 150 ns to 0.01% of a 10-V step including the time required for all internal nodes to settle after the hold command is given. Aperture uncertainty is less than 20 ps and linearity is 0.003%. The device has 10-pF on-chip hold and dummy capacitors and the die size is 8.548 mm/sup 2/ on a junction-field-effect-transistor (JFET) plus complementary bipolar process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Radiation Exposure During Ureteroscopy

Use of fluoroscopy during ureteroscopy increases the risk of radiation exposure to the urologist and patient. Radiation entrance dosages were measured at skin level in 37 patients, and at the neck, trunk and finger of the urologist, and neck and trunk of the circulating nurse. Radiation exposure time was measured in 79 patients, and was related to the purpose of the procedure and the type of ureteroscope used, whether rigid or flexible. Exposure could be minimized by decreasing the fluoroscopy time. A portable C-arm fluoroscopy unit with electronic imaging and last image hold mode should be used to minimize exposure time. Lead aprons and thyroid shields should be used by the urologist and other personnel in the endoscopy room.

The Ballast methodology for structured partial scan design

An efficient partial scan technique called Ballast (balanced structure scant test) is presented. Scan path storage elements (SPSEs) are selected such that the remainder of the circuit has certain desirable testability properties. A complete test set is obtained using combinatorial automatic test pattern generation (ATPG). Some SPSEs may need to be provided with a HOLD mode; their number is minimized by ordering the registers in the scan path and formatting the test patterns appropriately. This methodology leads to a low area overhead and allows 100% coverage of irredundant faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Peak-to-peak detector for the arterial pulsations in the plethysmogram. I: technical description and simulation.

A peak-to-peak detector for plethysmographic signals is described. This new detector measures the peak-to-peak value of the arterial pulsations in the plethysmogram, while the influence of volume variations in the peripheral vascular bed due to changing intrathoracic pressure is eliminated. Incorporated into the detector is a hold mode, which is entered if disturbances are detected. Simulation tests are presented.

A precision FET-less sample-and-hold with high charge-to-droop current ratio

A monolithic sample-and-hold amplifier designed without field-effect transistors is described. Various sample-and-hold configurations are compared and their merits are discussed. Unique features of the design include a diode-bridge switch and a current booster with 50 mA of drive capability to charge the hold capacitor during large signal acquisition. The output amplifier's operating conditions are changed under logic control; it functions as a fast follower in the sample mode, and as a low input current amplifier in the hold mode. Performance characteristics include: 3.5-/spl mu/s acquisition time to 0.1 percent with a 5000-pF hold capacitor, 50 pA of droop current from 0 to 70/spl deg/C, 10/SUP 9/ charge-to-droop current ratio, and 0.3 mV of zero-scale error.

A fast 6-bit ADC

A fast and economical ADC will be described that operates in track and hold modes up to 10 MHz, and requires a limited amount of components. Very fast ADCs with more than 6 bits are commercially available but they are quite expensive; if lower resolution is sufficient economical solutions are not readily available.

A high voltage source with digital control for dielectric measurements

An improvement in the rigorous control of high voltages for dielectric measurements is achieved by employing digital techniques in the development of a low-voltage controller for a generator of either the oscillator or electrostatic type. Principal advantages over a method previously described are the provision of a highly stable hold mode and the capability for very slow rates of voltage application. Comprehensive logic controls, incorporating essential safety features, allow fully automatic experiments to be performed, and a flexible design permits a simple addition to the equipment to increase the resolution if desired.

Contributions of the x-15 program to lifting entry technology

Entries from altitudes greater than 350,000 ft with the X-15 airplane have provided piloting experience and verification of predicted control characteristics and operational techniques. The airplane re-enters as a glider and duplicates several phases in the recovery of higher-performance vehicles, for example, transition from near-zero dynamic pressure to aerodynamic flight, and the terminal-area ranging and landing. During entries, reaction controls have been used to surprisingly high dynamic pressures. Rate command control provided satisfactory control, and hold modes were appreciated by the pilots for secondary control mocjes. With conservatively planned flights, the pilots have had no problem controlling range to base with contact navigation. Landmarks have been observed from above 300,000 ft and 160 miles range. The approach and landing of the low-lift-drag-ratio X-15 airplane has become routine, with relatively small dispersion in touchdown and slideout distance. The speed brakes have been an important control for regulation of ranging for landing; however, the pilots indicated that faster-acting speed brakes would allow more flexible operation. D 9 = L := q = Nomenelatu re drag acceleration due to gravity, ft/sec2 lift dynamic pressure, psf angle of attack, deg pitch angle, deg roll angle, deg yaw angle, deg