Hold Circuit Research Articles

An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.

MODELING OF ANALOG-TO-DIGITAL SIGNAL CONVERTERS FOR SENSOR MICROSYSTEMS IN THE MICROWIND SOFTWARE

For the results of simulating the operation of analog-digital converters, we chose such a converter as the serial approximation ADC (SAR ADC). A sequential approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform to a discrete digital representation by binary search through all possible quantization levels before finally converging on a digital output for each conversion. There are three important blocks in the SAR ADC architecture: the sample and hold circuit (Sample and Hold, S/H), the comparator, and the SAR block. The topology and principle of operation of which was modeled in the Micro Wind software environment.

500 MS/s 4-Bit Flash ADC with Complementary Architecture

This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 V<sub>pp</sub> operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and preamp circuits corresponding to the analog stages are designed using complementary architecture to attain a sufficient swing range even at a low supply voltage. Notably, the proposed structure satisfies the error requirements. The error source of the flash ADC, such as the comparator’s input referred offset, did not degrade its performance, while the use of a calibration circuit, characterized by power consumption and area burdens and increased complexity, could also be avoided. Therefore, the proposed flash ADC met the error requirements, such as the comparator’s input referred offset, without the need for calibration circuits. The chip, fabricated using the TSMC 65 nm process, covers an area of 1,160 × 950 μm<sup>2</sup> and consumes 78 mW of power. Furthermore, its signal-to-noise and distortion ratio and spurious-free dynamic range were measured to be 23.36 dB and 30.26 dB, respectively, at a sampling frequency of 500 MHz.

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

Modeling, Prediction, and Results Correction of PDSH Circuits for Nanosecond Pulse Peak Detection

The peak detect and sample hold (PDSH) circuit is an important component of the light detection and ranging (LiDAR) system, because the PDSH circuit can correct the walk error of the time discriminator, and distinguish different objects at the same location. However, due to the requirement for high-precision measurement of nanosecond-scale pulse signals, the design of the PDSH circuit presents significant challenges. This paper accomplishes the modeling of the PDSH circuit, including the modeling of the PDSH measurement speed and the voltage step, quantifies various factors that affect the PDSH circuit measurement results, and makes predictions based on the model. Through the derivation and simplification of the rise process in the PDSH circuit, this study establishes a mathematical model to predict the performance of the PDSH circuit. Furthermore, this study also investigates the effect of circuit delay time on the measurement speed of the PDSH circuit. Meanwhile, this study analyzes the voltage step process, and an equivalent circuit model is derived through theoretical analysis. By utilizing a fitting method, the equivalent capacitance value of the diode is obtained. The simulation and experiment results show that the errors between the measurement speed model of the PDSH circuit and the actual circuit are no more than 1.98 ns and 2.03 ns, respectively. Thus, the measurement speed model can accurately predict whether the PDSH circuit meets the requirements. Moreover, the maximum absolute error of the equivalent circuit model is 19.87 mV, which can significantly reduce the error caused by the voltage step.

Analysis of Bandwidth Reduction and Resolution Improvement for Photonics-Assisted ADC

To keep pace with increasing data rates in the worldwide communication networks and the increased bandwidths requirements in measurement devices, sensors, radar, and many other applications, photonics-assisted analog-to-digital converters (PADCs) may be promising alternatives to circumvent the bandwidth bottleneck in pure electronic analog-to-digital converters (EADCs). Here we analyze optical sub-Nyquist orthogonal sampling with sinc-pulse sequences for the time-interleaving of high-bandwidth input signals into parallel low-bandwidth sub-signals (first sampling stage). These sub-signals are then detected and further processed with low-bandwidth electronic devices in parallel branches (second sampling stage). Orthogonal sampling with ideal devices is error-free. Additionally, in contrast to electronic sample and hold circuits, the first sampling stage is based on a multiplication and not a switching. Therefore, it adds no aperture jitter and the low jitter of today's oscillators can be directly transferred to the sampling of high-bandwidth signals. Compared to the direct detection, in simulations and a proof of concept experimental demonstration, we show around 8.5 dB signal-to-noise and distortion (SINAD) and 1.4 bit effective number of bits (ENOB) improvement for the detection of a 14.5 GHz signal with the proposed method in a three-branch system. With further simulations we analyze the possibilities and limits of the method and derive an equation for the resolution. In a nine-branch system with a jitter of 10 fs for the oscillator and 100 fs for the electronics, 100 GHz input signals can be processed with a resolution of 6 bit in 11 GHz electronics, for instance. The scheme is only based on a modulator and standard RF equipment. Therefore, integration into a single chip, together with the following electronic ADCs is straightforward.

SpacePix3: SOI MAPS detector for space radiation monitoring

The SpacePix3 monolithic active pixel sensor is a novel ASIC for space radiation monitoring designed in a 180 nm SOI CMOS technology. The detector is capable of detecting and differentiating protons, electrons, and heavy ions. Its active sensor area is 3.84×3.84 mm2, pixel matrix is arranged in a 64×64 square array with 60 µm pitch. The pixel front-end amplifier signal range is 1–80 ke-, extended up to 30 Me- using a backside channel. Diodes integrated in the handle wafer in each pixel are biased at -150 V, creating a depleted layer approximately 35 µm deep. Impinging particle generates a charge pulse converted to a voltage pulse by the charge-sensitive amplifier. Maximum voltage memorized by the peak detector hold circuit is digitized using on-chip 10-bit asynchronous column SAR ADCs. Two readout interfaces are available, 400 MHz LVDS and 50 MHz SPI. Total current consumption is 31 mA from a 1.8 V power supply in the SPI mode.

An ultra‐low quiescent current tri‐mode DC–DC boost converter with 95.6% peak efficiency for internet of things application

AbstractAn ultra‐low quiescent current tri‐mode DC–DC boost converter is proposed in this paper, which can efficiently handle loads from 1 μA to 300 mA, providing 5‐V output from 3 to 4.2‐V input. Hysteresis current mode control is adopted to realize seamless mode switching between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In order to deal with the light load situation, this paper proposes a quasi burst mode (QBM). In this mode, most of the modules are turned off and only the QBM controller, low‐power current bias and sample and hold circuit are retained, which significantly reduces the static current of the converter, and thus improves the light load efficiency. Meanwhile, the average current of error amplifier and comparator are reduced significantly by dynamic biasing. Finally, the efficiency of the converter is greatly improved and kept at a reasonable output ripple. The proposed converter is implemented in a 0.13‐μm BCD process design and manufacturing. The test results show that the quiescent current of the converter is only 780 nA, which can achieve a peak efficiency of 95.6%, and ensure that the efficiency is maintained above 80% in the load range of 10 μA to 300 mA.

A Review of Techniques to Enhance an Amplifier’s Performance Using Resistive Local Common Mode Feedback

A review of some of the most common applications of the resistive local common mode feedback technique to enhance amplifier’s performance is presented. It is shown that this simple technique offers essential improvement in open loop gain, gain-bandwidth product, slew rate, common mode rejection ratio, power supply rejection ratio, etc. This is achieved without increasing power dissipation or supply voltage requirements and with small additional silicon area and circuit complexity. It is also shown that it is especially appropriate to improve amplifiers’ performance in current fine-line submicrometer CMOS technology. Some of the applications discussed are GB enhanced, class AB and super class AB operational amplifiers, gain boosted op-amps, bulk-driven circuits, sample and hold circuits and power management circuits, among others.

Nanosecond Peak Detect and Hold Circuit With Adjustable Dynamic Range

Nanosecond Peak Detect and Hold Circuit With Adjustable Dynamic Range

A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces

This brief presents a single-ended (SE) receiver (RX) with a self-referenced (SR) technique using sample and hold (S&H) circuits. The proposed RX does not require a reference voltage (VREF) for data recovery by comparing the present data with previous data. The RX was implemented as half-rate architecture to halve the clock frequency and facilitate the S&H operation. Moreover, the proposed decision feedback equalizer (DFE) is suitable for SR RX and improves the reliability of RX by eliminating inter-symbol interference (ISI). The prototype RX, fabricated using 28-nm CMOS technology, occupies a 0.0016 mm2 active area. The measurement result of the proposed RX achieves a bit-error-rate (BER) under 10−12 with a 15-Gb/s data rate in a 17-inch PCB FR4 channel. The RX consumes 13.56 mW of power and has a power efficiency of 0.90 pJ/bit.

SpacePix2: SOI MAPS detector for space radiation monitoring

The SpacePix2 monolithic active pixel sensor (MAPS) is a novel ASIC for space radiation monitoring designed in a 180 nm SOI CMOS technology. The active sensor area is 3.84 × 3.84 mm2, pixel matrix is arranged as a 64 × 64 array with 60 µm pitch. The pixel front-end amplifier signal range is 2–80 ke−, extended up to 30 Me− using a backside channel. Diodes integrated in the handle wafer in each pixel are biased at −150 V. Impinging particle generates a charge pulse converted to voltage pulse by charge sensitive amplifier (CSA). Maximum voltage memorized by the peak detector hold (PDH) circuit is digitized using on-chip 10-bit asynchronous column SAR ADCs. Two readout interfaces are available, 400 MHz LVDS and 50 MHz SPI. Total power consumption is 43 mA from a 1.8 V power supply. The ASIC has been tested in space in low Earth orbit (LEO) and sample data are shown.

A 1.5 V 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique

This brief presents a track and hold (T/H) circuit for time-interleaved analog-to-digital converters based on a new linearization technique—time-divided post-distortion cancellation. Fabricated in 65 nm CMOS, it achieves 82.1 dB SFDR with a 700-mV near-Nyquist input at a clock speed of 2 GS/s, while drawing only 9 mW power from a 1.5-V supply. Compared to the previous state-of-the-art circuits, this T/H circuit exhibits an energy-efficiency figure-of-merit improvement of 9.5 dB.

A fully digital open‐loop clock and data synchronizer for ultra‐low power super‐regenerative receivers

SummaryIn this paper, a clock and data synchronizer (CDS) is presented to improve channel selectivity of digitally assisted super‐regenerative receivers (SRRs). The proposed CDS performs phase and frequency adjustment of the quench signal using a fully digital open‐loop architecture removing the need for conventional phase‐locked loop (PLL) architectures. The required signal shaping of the recovered data is also performed by the proposed CDS to restore the nonreturn‐to‐zero data format without using any pulse width expander or sample and hold circuit. A multichannel SRR is implemented employing the proposed CDS where a Q‐enhancement procedure is also adopted to further improve the channel selectivity. The proposed SRR operates at 2.4‐GHz ISM band and supports a data rate of 1 Mb/s, while the sensitivity is about −88 dBm, and the selectivity is better than −18 dB at a 10‐MHz offset frequency. Implemented using a 0.18‐μm standard CMOS process and with a 1.1‐V supply voltage, the proposed SRR consumes about 0.4 mW.

Cooperative Spacing Sampled Control of Vehicle Platoon Considering Undirected Topology and Analog Fading Networks

The work on this paper studies the combined effect of vehicle dynamics, sampling period and the quality of inter-vehicle sensing and communication on the performance of platoon control. First, we induce the sampled control protocol from continuous–time linear consensus protocol by employing zero–order hold circuit and periodic sampling technology, then by virtue of the obtained sampled control protocol, the continuous–time platoon system is equivalently transformed into a discrete–time system. Second, for the inter–vehicle communication with ideal channel and under undirected information flow topology (UIFT), the stability thresholds of control gains are explicitly established by solving a discrete–time simultaneous stabilization problem, bilinear transformation and the Routh-Hurwitz stability criterion. Meanwhile, to ensure the fastest asymptotic stability of the platoon dynamics, we propose an optimal asymptotic convergence factor and a correspondingly optimal sampled control protocol. Third, For the inter–vehicle communication with identical fading networks and under UIFT, through solving a modified Riccati inequality, we provide a sampled control protocol depending not only on information flow topology (IFT) and sampling period, but also on the statistics of the inter–vehicle communication channel. Besides, employing Lyapunov inequality in probability theory, we show a necessary condition for the sampled control protocol ensuring the platoon dynamics mean square stable. Finally, simulations are performed to demonstrate the theory’s discoveries.

A PFM Boost Harvester With System-Level Self-Tuned Maximum Power Point Tracking

This article presents a low-overhead energy harvesting and delivery system (EHDS) with pulse frequency modulated (PFM) integrated voltage regulator (IVR) power conversion and self-tuned maximization of system output power. A novel load-inclusive time-based maximum power point tracking (LI-TB-MPPT) is developed to provide centralized tuning of PFM-IVR operation based on both source capabilities and load demand on-the-fly, and a configurable fractional sample and hold circuit provides adaptive harvesting window control. The proposed EHDS enables robust harvesting while relieving the use of high passives, with over two orders of magnitude reduction, at the cost of only slight decrease in end-to-end efficiency compared to prior works. Furthermore, a low-overhead wake-up assist circuit utilizes cold-configuration of harvesting sources for efficient and accelerated cold-start. The proposed EHDS is demonstrated in a 65 nm CMOS process with commercial photovoltaic energy harvesting modules. Using only 1.2 and 1 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>H of passives, measured results show a peak 74.9&#x0025; end-to-end efficiency (simulated up to 85&#x0025; at 47<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>H) and a fast startup time of 3.8 ms. Up to 15&#x0025; increase in conversion efficiency against load and input voltage variations is achieved with LI-TB-MPPT. The results demonstrate a compact solution for self-sustained cost-restricted stand-alone systems.

Suboptimal State Tracking Control Applied to a Nonlinear Fractional-Order Slewing Motion Flexible Structure

Abstract The control of slewing motion flexible structures is important to a number of systems found in engineering and physical sciences applications, such as aerospace, automotive, robotics, and atomic force microscopy. In this kind of system, the controller must provide a stable and well-damped behavior for the flexible structure vibrations, with admissible control signal amplitudes. Recently, many works have used fractional-order derivatives to model complex and nonlinear dynamical behavior present in the mentioned systems. In order to perform digital computer-based control of fractional-order dynamical systems, a time discretization of the equations is necessary. In many cases, the Grünwald–Letnikov method is used, resulting in an implicit integration method. In this work, a nonlinear slewing motion flexible structure is modeled considering a fractional-order viscous damping in the flexible beam motion. To obtain an explicit integration method, based on the Grünwald–Letnikov definition, the discretization of the dynamical equations is performed considering the existence of sample and hold circuits. In addition, real-time suboptimal infinite horizon tracking control system strategies, namely, the linear quadratic tracking and the state-dependent Riccati equation tracking controller, are designed and implemented to control the fractional-order slewing motion flexible system. The general behavior and performance of the control systems are tested for parameter uncertainties related to the order of the fractional derivatives.

Multiplexed Readout for an Experiment with a Large Number of Channels Using Single-Electron Sensitivity Skipper-CCDs.

This paper presents the implementation of a multiplexed analog readout electronics system that can achieve single-electron counting using Skipper-CCDs with non-destructive readout. The proposed system allows the best performance of the sensors to be maintained, with sub-electron noise-level operation, while maintaining low-bandwidth data transfer, a minimum number of analog-to-digital converters (ADC) and low disk storage requirement with zero added multiplexing time, even for the simultaneous operation of thousands of channels. These features are possible with a combination of analog charge pile-up, sample and hold circuits and analog multiplexing. The implementation also aims to use the minimum number of components in circuits to keep compatibility with high-channel-density experiments using Skipper-CCDs for low-threshold particle detection applications. Performance details and experimental results using a sensor with 16 output stages are presented along with a review of the circuit design considerations.

A Dual-Domain Dynamic Reference Sensing for Reliable Read Operation in SOT-MRAM

Although spin orbit torque magnetic random access memory (SOT-MRAM) is one of the strong candidates for next-generation embedded memories, the degradation of read margin due to low tunnel magnetoresistance ratio (TMR) with process variations has been a large concern. In this paper, we present the dual-domain dynamic reference (DDDR) sensing scheme, where the reference voltage can be dynamically changed based on the combined voltage and time domain sensing to increase the sensing margin. The Half Schmitt trigger and sample & hold circuits are efficiently employed to generate data-dependent reference voltages and to store the sampled voltage levels at different times, respectively. According to the simulations using 28nm CMOS technology with 128 by 128 SOT-MRAM array, the proposed DDDR approach achieves a 243mV of sensing margin under 6.08E-8 bit-error-rate (BER) at 1.76ns, which is 2X larger margin with more than 100 times lower BER compared to the conventional read scheme. When scaling down the pre-charge voltage, the proposed scheme achieves more than 50% of the read energy savings under 1E-5 target BER condition.

A CMOS Integrator-Based Clock-Free Time-to-Digital Converter for Home-Monitoring LiDAR Sensors.

This paper presents a nine-bit integrator-based time-to-digital converter (I-TDC) realized in a 180 nm CMOS technology for the applications of indoor home-monitoring light detection and ranging (LiDAR) sensors. The proposed I-TDC exploits a clock-free configuration so as to discard clock-related dynamic power consumption and some notorious issues such as skew, glitch, and synchronization. It consists of a one-dimensional (1D) flash TDC to generate coarse-control codes and an integrator with a peak detection and hold (PDH) circuit to produce fine-control codes. A thermometer-to-binary converter is added to the 1D flash TDC, yielding four-bit coarse codes so that the measured detection range can be represented by nine-bit digital codes in total. Test chips of the proposed I-TDC demonstrate the measured results of the 53 dB dynamic range, i.e., the maximum detection range of 33.6 m and the minimum range of 7.5 cm. The chip core occupies the area of 0.14 × 1.4 mm2, with the power dissipation of 1.6 mW from a single 1.2-V supply.