Abstract
SummaryIn this paper, a clock and data synchronizer (CDS) is presented to improve channel selectivity of digitally assisted super‐regenerative receivers (SRRs). The proposed CDS performs phase and frequency adjustment of the quench signal using a fully digital open‐loop architecture removing the need for conventional phase‐locked loop (PLL) architectures. The required signal shaping of the recovered data is also performed by the proposed CDS to restore the nonreturn‐to‐zero data format without using any pulse width expander or sample and hold circuit. A multichannel SRR is implemented employing the proposed CDS where a Q‐enhancement procedure is also adopted to further improve the channel selectivity. The proposed SRR operates at 2.4‐GHz ISM band and supports a data rate of 1 Mb/s, while the sensitivity is about −88 dBm, and the selectivity is better than −18 dB at a 10‐MHz offset frequency. Implemented using a 0.18‐μm standard CMOS process and with a 1.1‐V supply voltage, the proposed SRR consumes about 0.4 mW.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of Circuit Theory and Applications
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
