High Mobility Substrates Research Articles

Plasmonics-enhanced photoconductive terahertz detector pumped by Ytterbium-doped fiber laser

We present a photoconductive terahertz detector operating at the 1 µm wavelength range at which high-power and compact Ytterbium-doped femtosecond fiber lasers are available. The detector utilizes an array of plasmonic nanoantennas to provide sub-picosecond transit time for the majority of photo-generated carriers to enable high-sensitivity terahertz detection without using a short-carrier-lifetime substrate. By using a high-mobility semiconductor substrate and preventing photocarrier recombination, the presented detector offers significantly higher sensitivity levels compared with previously demonstrated broadband photoconductive terahertz detectors operating at the 1 µm wavelength range. We demonstrate pulsed terahertz detection over a 4 THz bandwidth with a record-high signal-to-noise ratio of 95 dB at an average terahertz radiation power of 6.8 µW, when using an optical pump power of 30 mW.

PEALD grown high-k ZrO2 thin films on SiC group IV compound semiconductor

The study of ZrO2 thin films on SiC group IV compound semiconductor has been studied as a high mobility substrates. The ZrO2 thin films were deposited using the Plasma Enhanced Atomic Layer Deposition System. The thickness of the thin films were measured using ellipsometer and found to be 5.47 nm. The deposited ZrO2 thin films were post deposition annealed in rapid thermal annealing chamber at temperature of 400°С. The atomic force microscopy and X-гау photoelectron spectroscopy has been carried out to study the surface topography, roughness and chemical composition of thin film, respectively.

PEALD grown high-k ZrO-=SUB=-2-=/SUB=- thin films on SiC group IV compound semiconductor

The study of ZrO2 thin films on SiC group IV compound semiconductor has been studied as a high mobility substrates. The ZrO2 thin films were deposited using the Plasma Enhanced Atomic Layer Deposition System. The thickness of the thin films were measured using ellipsometer and found to be 5.47 nm. The deposited ZrO2 thin films were post deposited annealed in rapid thermal annealing chamber at temperature of 400oC. The atomic force microscopy and x-ray photoelectron spectroscopy has been carried out to study the surface topography and roughness and chemical composition of thin film respectively. DOI: 10.21883/FTP.2017.01.8125

Higher-k Tetragonal Phase Stabilization in Atomic Layer Deposited Hf1-xZrxO2 (0<x<1) Thin Films on Al2O3 Passivated Epitaxial-Ge

ABSTRACTFor exploring the prospect of higher-k dielectric phase engineering on a high mobility substrate, films of Hf1-xZrxO2 with varying x-values (0 ≤ x ≤ 1) were deposited on Al2O3 passivated Ge substrates using atomic layer deposition (ALD) with a cyclic deposit-anneal-deposit-anneal (DADA) scheme. The evolution of monoclinic to higher-k tetragonal structure with increasing ZrO2 concentration was probed by grazing incident x-ray diffraction and partial reciprocal space maps using the highly brilliant synchrotron x-ray source at the Cornell High Energy Synchrotron Source (CHESS). A primarily amorphous/nano-crystalline matrix of the asdeposited films changed to randomly aligned grains of nanocrystalline MO2 (M=Hf, Zr) after post deposition annealing at 800 °C for 200 seconds. In contrast, the DADA films annealed for same thermal budget showed high degree of preferred orientation along certain crystallographic directions. With increasing ZrO2 content, the structure of the films changed from a monoclinic to a tetragonal phase. A lower amount of ZrO2 (x = 0.33) was required for stabilizing the tetragonal phase in films grown on Al2O3 passivated Ge substrate as compared to similar films grown on a Si substrate via the same DADA process (x ≥ 0.50).

Review—Device Assessment of Electrically Active Defects in High-Mobility Materials

The stringent device performance specifications of advanced scaled down technologies necessitates the implementation of high mobility substrates such as SiGe, Strained Si (sSi), Ge, sGe and/or III-V materials like GaAs, InGaAs. The control of the stress-induced defects remains a key challenge. Simple device structures such as capacitors, diodes and transistors are used to assess the electrical activity of extended defects (dislocations; antiphase boundaries; …) in high-mobility channel materials. Beside junction current analyses and lifetime studies, also the use of low-frequency noise characterization is reported. Special case studies are discussed to illustrate the used methodology. The potential of TCAD studies to better understand the electrical defect activity is also briefly addressed.

The demonstration of colossal magneto-capacitance effect with the promising gate stack characteristics on Ge (100) by the magnetic gate stack design

The tetragonal-phase BaTiO3 as the high dielectric (HK) layer and the magnetic FePt film as the metal gate (MG) are proposed to be the gate stack scheme on the Ge (100) substrate. The ∼75% dielectric constant (κ-value) improvement, ∼100X gate leakage (Jg) reduction, and the promising Jg-equivalent-oxide-thickness (EOT) gate stack characteristics are achieved in this work with the colossal magneto-capacitance effect. The perpendicular magnetic field from the magnetic FePt MG film couples and triggers the more dipoles in the BaTiO3 HK layer and then results in the super gate capacitance (Cgate) and κ-value. Super Jg-EOT gate stack characteristics with the magnetic gate stack design on the high mobility (Ge) substrate demonstrated in this work provides the useful solution for the future low power mobile device design.

(Invited) High Pressure Sputtering for High-K Dielectric Deposition. Is It Worth Trying

(Invited) High Pressure Sputtering for High-K Dielectric Deposition. Is It Worth Trying

(Electronics & Photonics Division Award Presentation) Si-SiO2 Interface to High-K-Ge/III-V Interface: Passivation and Reliability

The Si-SiO2 interface is one of the most important semiconductor-dielectric interfaces that has been studied extensively over many decades. The understanding and control of structural and electronic properties of Si-SiO2 interfaces has provided many clues for technological advancement. The article discusses how the Si-SiO2 interface migrated through the technological landscape like plasma processing damage, hot carrier effects and negative bias temperature instability (NBTI) and subsequent passivation techniques using hydrogen to nitrogen. Introduction of high-k gate dielectrics brought significant attention to the interface between silicon and high-k dielectrics but Si-SiO2 interface continued to be important because of the presence of a SiO2-based interfacial layer. With deposition of high-k gate dielectrics high carrier mobility substrates (Ge/III-V) are currently being considered as the channel materials. To obtain a high quality interface between the high-k dielectrics and the high mobility substrates some issues like deposition process, precise selection of deposition parameters, predeposition surface treatments, appropriate passivation techniques and subsequent annealing temperatures are also outlined.

ALD deposited ZrO2 ultrathin layers on Si and Ge substrates: A multiple technique characterization

In this study, a multiple characterization technique of ultrathin ZrO2 films, deposited on high mobility substrates such as strained-Si (s-Si) and p-type Ge (p-Ge) by Atomic Layer Deposition (ALD), is presented. For reasons of comparison ZrO2 films on p-type Si (p-Si) where also studied. The stoichiometry, chemical composition and valence band electronic structure are characterized by X-ray Photoelectron Spectroscopy (XPS). For p-Si and s-Si substrates the ZrO2 valence band edge is found at 2.4±0.2eV while for the p-Ge substrate, the valence band edge is found at 2.6±0.2eV. Furthermore, Atomic Force Microscopy (AFM) measurements reveal that, all tested samples are in general smooth (0.2–0.3nm roughness) and uniform. MOS capacitive structures were fabricated, using Al as a gate metal, and characterized electrically through C–V and G–V measurements. The typical behavior of a MOS structure has been revealed. Dit values, of the order of 1012eV−1cm−2, were calculated using Hill–Coleman method.

Quantification of interfacial state density (Dit) at the high-k/III-V interface based on Hall effect measurements

In this work, we propose a method to quantify the density of interfacial states at the oxide/semiconductor interface using only Hall concentration and low frequency capacitance-voltage data. We discuss the advantages of the proposed method over commonly used admittance techniques in characterizing highly disordered interfaces between the high-k dielectric and high mobility substrates. This gated Hall method is employed to characterize high-k/IIIV interface quality in metal-oxide semiconductor high electron mobility transistor structures with high mobility InGaAs channels.

(Invited) Scanning Probe Analysis of Dielectrics on High Mobility Substrates

In this work we employ electrical scanning probe techniques to evaluate on a nanoscale the influence of semiconductor surface morphology on the electrical properties of dielectrics. Gate leakage, reliability and oxide thickness uniformity are assessed by conductive atomic force microscopy (C-AFM). Interface traps are analyzed by scanning capacitance microscopy (SCM). A correlation between nanoscale and macroscale trends is established following reverse processing of the devices. The impact of surface morphology on localized dielectric properties is evaluated by studying MOSFETs having the same silicon channel strain but different dielectric/substrate interface roughness. The correlation between surface morphology, leakage and SCM signal suggests that for dielectrics on high mobility substrates prone to surface roughening, the morphology as well as the dielectric itself play a role in the final dielectric quality. Optimized epitaxial growth will therefore enable improved device performance, reliability and variability. The results have implications for all technologies which employ relaxed SiGe templates.

Achieving Ultra-Shallow Junctions in Future CMOS Devices by a Wet Processing Technique

The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs and high mobility substrates, including compound semiconductors (III-V). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under low thermal budget environments for III-V materials. Ion implantation into III-V materials presents a problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. This paper presents a potentially defect-free alternative, mono-layer doping (MLD), which utilizes wet processing techniques.

A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ and InP Capacitors

By taking into account simultaneously the effects of border traps and interface states, the authors model the alternating current capacitance-voltage (C-V) behavior of high-mobility substrate metal-oxide-semiconductor (MOS) capacitors. The results are validated with the experimental In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/ high-κ and InP/high-κ (C-V) curves. The simulated C-V and conductance-voltage (G-V) curves reproduce comprehensively the experimentally measured capacitance and conductance data as a function of bias voltage and measurement frequency, over the full bias range going from accumulation to inversion and full frequency spectra from 100 Hz to 1 MHz. The interface state densities of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As and InP MOS devices with various high-κ dielectrics, together with the corresponding border trap density inside the high-κ oxide, were derived accordingly. The derived interface state densities are consistent to those previously obtained with other measurement methods. The border traps, distributed over the thickness of the high- κ oxide, show a large peak density above the two semiconductor conduction band minima. The total density of border traps extracted is on the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . Interface and border trap distributions for InP and In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As interfaces with high-κ oxides show remarkable similarities on an energy scale relative to the vacuum reference.

(Invited) Issues and Challenges of High-k Dielectrics on High-Mobility Substrates

With the current trend in device scaling, for high speed and low power applications materials with high-k dielectric constant such as Hf-based dielectrics are being integrated into standard CMOS technologies. Hihg mobility substrates such as germanium (Ge) and gallium arsenide (GaAs) are being considered for their high electron mobility. The interface between the high-k dielectrics and the high mobility substrates are not well understood. A strong interface passivation technique is, therefore, necessary to optimize the device performance. As it is clear from the electrical performance in these devices depends on the deposition process, precise selection of deposition parameters, predeposition surface treatments and subsequent annealing temperatures. This work reviews the recent developments of high-k/Ge interface and its characterization. To form an electrically passive interface, interface treatments such as surface nitridation of HfO2/Ge interface will be evaluated. In addition, electrical characteristics of high-k on III-V substrates are also outlined.

(Invited) Active Trap Determination at the Interface of Ge and In0.53Ga0.47 as Substrates with Dielectric Layers

Due to the high carrier mobility, Ge and III-V semiconductors are attractive as active channels for post-Si metal oxide semiconductor (MOS) devices. However, integration of gate dielectrics on high-mobility substrates is frequently jeopardized by the electrical activity of traps nearby the interface. Active traps determination at the interface between the two semiconductors with gate dielectrics has been conducted with the aim to validate several electrical passivation methodologies. In particular, GeO2 and LaGeOx passivations of Ge are investigated by conjugating magnetic resonance spectroscopy and electrical response of the MOS capacitors. The case of In0.53Ga0.47As is addressed by tailoring the surface treatments and the growth parameters in the trimethyaluminum based atomic layer desposition of Al2O3 films. The electrical quality of the Al2O3/In0.53Ga0.47As interface is assessed by exploring the temperature dependent electrical response of the MOS capacitors and admittance spectroscopy of the active traps energetically distributed in the In0.53Ga0.47As bandgap.

Issues and Challenges of High-κ Dielectrics on High-Mobility Substrates

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Electrical and Structural Properties of Ternary Rare-Earth Oxides on Si and Higher Mobility Substrates and their Integration as High-k Gate Dielectrics in MOSFET Devices

The continuous downscaling in metal-oxide-semiconductor field effect transistors is approaching fundamental limits. Allied to new device architectures, novel materials are needed in order to continue the evolution of complementary metal-oxide-semiconductor technologies. The combination of high dielectric constant (k) oxides with silicon and other semiconductors having a higher charge carrier mobility (ex.: germanium) is currently a fundamental technologic issue that requires extensive investigation on materials science. The search for high-k oxides (with k > 20) that can offer stable interfaces combined with a low density of electrically active defects is a topic of major interest. In this contribution, we will review some of our results on the structural and electrical properties of REScO3 (RE = La, Gd, Tb, Sm) and LaLuO3 amorphous films on Si as well as on high mobility substrates, showing their potential as high-k dielectrics for future CMOS applications.

Magnetic resonance spectroscopy of defects at the dielectric-semiconductor interface: Ge substrates and Si nanowires (invited)

High mobility substrates and silicon nanowires are important key elements in the development of advanced devices targeting a vast range of functionalities. In almost all applications the interface between the semiconductor and the oxide layer placed on top or all around plays a crucial role in determining the device performance. The investigation of defects at these interfaces is therefore mandatory to fully exploit the advantages of these systems. We report on the application of electrically detected magnetic resonance (EDMR) techniques in the investigation of defects at the interface between Ge and GeO 2 (or GeO x ) and at the interface between silicon nanowires (SiNWs) and SiO 2.

Electrical Characterization of the MOS (Metal-Oxide-Semiconductor) System: High Mobility Substrates

Recent developments on CMOS-driven III-V and Ge MOS (Metal-oxide-semiconductor) technologies provide new opportunities in advancing the performance envelope of MOS device as well as the relevant electrical characterization techniques. Understanding the capacitance-voltage (CV) and conductance voltage (GV) responses of the III-V/Ge MOS devices can lead to better assessments of the oxide-semiconductor material systems and more accurate performance predictions.

On the High-Field Transport and Uniaxial Stress Effect in Ge PFETs

Ge is one of the promising candidates for high-mobility channel material in future complementary metal-oxide-semiconductor technology. High-field transport in short-channel Ge p-channel field-effect transistors (PFETs) needs to be examined since device performance is determined by high-field velocity in quasi-ballistic transport regime. In this paper, ballisticity and the relationship between carrier velocity and mobility in short-channel (70-nm) Ge PFETs were thoroughly investigated. A 1.6 × -2× higher velocity was confirmed in Ge PFETs than that in Si PFETs. Uniaxial stress is also a strong performance booster besides high-mobility substrate. The effectiveness of the uniaxial stress to velocity enhancement in Ge PFETs was experimentally demonstrated in short channel regime. A 1.4× higher drive current can be achievable by uniaxially strained Ge PFET in ballistic transport regime as compared with strained Si PFET.