Abstract
In this work we employ electrical scanning probe techniques to evaluate on a nanoscale the influence of semiconductor surface morphology on the electrical properties of dielectrics. Gate leakage, reliability and oxide thickness uniformity are assessed by conductive atomic force microscopy (C-AFM). Interface traps are analyzed by scanning capacitance microscopy (SCM). A correlation between nanoscale and macroscale trends is established following reverse processing of the devices. The impact of surface morphology on localized dielectric properties is evaluated by studying MOSFETs having the same silicon channel strain but different dielectric/substrate interface roughness. The correlation between surface morphology, leakage and SCM signal suggests that for dielectrics on high mobility substrates prone to surface roughening, the morphology as well as the dielectric itself play a role in the final dielectric quality. Optimized epitaxial growth will therefore enable improved device performance, reliability and variability. The results have implications for all technologies which employ relaxed SiGe templates.
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