High Etch Selectivity Research Articles

Mechanism of Improving Etching Selectivity for E-Beam Resist AR-N 7520 in the Formation of Photonic Silicon Structures

The selectivity of the reactive ion etching of silicon using a negative electron resist AR-N 7520 mask was investigated. The selectivity dependencies on the fraction of SF6 in the feeding gas and bias voltage were obtained. To understand the kinetics of passivation film formation and etching, the type and concentration of neutral particles were evaluated and identified using plasma optical emission spectroscopy. Electron temperature and electron density were measured by the Langmuir probe method to interpret the optical emission spectroscopy data. A high etching selectivity of 8.0 ± 1.8 was obtained for the etching process. The optimum electron beam exposure dose for defining the mask was 8200 pC/m at 30 keV.

Characteristics of clean SiO2 atomic layer etching based on C6F6 physisorption

SiO2 atomic layer etching (ALE) techniques are widely used to improve the etch issues related to nanoscale semiconductor device etching such as self-aligned contact (SAC) etching requiring high etch selectivity of SiO2/Si3N4. For more precise and cleaner SiO2 ALE, cryo-ALE methods using physisorption of fluorocarbon gas at a cryotemperature are also being investigated. In this study, to avoid the use of cryotemperature for clean SiO2 ALE, a high boiling point (HBP) gas such as C6F6, having 80 °C of boiling point (global warming potential: 7), has been used as the physisorption gas without using cryotemperatures. At a substrate temperature lower than −15 °C, due to the adequate physisorption of C6F6 on the SiO2 and Si3N4 surfaces, high SiO2 etch depth per cycle (EPC) and high etch selectivity of SiO2/Si3N4 could be achieved through the higher chemical reaction of the fluorocarbon layer with SiO2 than that of Si3N4. For the etching of Si3N4 line patterned SiO2, an O2 descumming step was added after every 50 cycles of ALE process to prevent fluorocarbon layer deposition on the sidewall of the Si3N4 mask. Finally, anisotropic SiO2 etch profiles with high etch selectivity of SiO2/Si3N4 could be obtained without contamination of chamber sidewalls.

A Comprehensive Study of NF3-Based Selective Etching Processes: Application to the Fabrication of Vertically Stacked Horizontal Gate-All-around Si Nanosheet Transistors.

In this paper, we demonstrate a comprehensive study of NF3-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF3/O2/Ar gas mixture is used to etch back the SiN film. The impact of the O2/NF3 ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O2 into NF3/Ar discharge, the selectivity increases sharply, but when the ratio of O2/NF3 is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O2/NF3 = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm.

Novel Wet Etchant for Highly Selective Etching of Si1-XGex-Film to Si-Film with Sodium Periodate Oxidant

As the technology node of complementary-metal-oxide-semiconductor (CMOS) transistor has been scaled down to 3 nm, CMOS transistor’s structure has been changed from fin field-effect transistors to gate-all-around field-effect transistors (GAAFETs) to improve the short-channel effects by enhancing gate controllability. In addition, dynamic random-access memory (DRAM) also has been faced the limitation in scaling-down of a capacitor having high aspect ratio and in migrating from 6 to 4F2 cell increasing floating body effects. To overcome the limitation, 3-dimensional (D) DRAM structure having GAA structure has been researched as an alternative structure to the conventional 6F2 cell structure. In fabricating GAAFETs and 3-D DRAM, two major fabrication processes are needed, i) epitaxial growth of Si1-xGex/Si multi-stacks, and ii) selective etching of Si1-xGex films to Si films. For process i), low Ge concentration (<30%) is desirable for reducing stacking faults and defects at the interfaces between Si1-xGex and Si. In addition, for process ii), considerably high etch rate (>30nm/min) and etch selectivity of Si1-xGex films to Si films (>300:1) are required. In particular, for etching Si1-xGex grown on Si layer of a sacrificial layer, a high selectivity, high etch rate and isotropy of wet chemical etching are strongly required. In general, among the components of wet chemical etchant consisting of oxidant, etching accelerator (i.e., HF), selectivity enhancing agent (i.e., acetic acid), and deionized water, the higher standard reduction potential (SRP) of oxidant leads the higher selectivity and higher etch rate of Si1-xGex films to Si films due to the increase in the potential differences of SRP and Si1-xGex valence band edge. For the case of a conventional wet etchant using peracetic acid (PAA) or hydrogen peroxide (H2O2) as an oxidant, their SRP are ~1.75 and ~0.69 eV, respectively. However, its selectivity and etch rate of Si1-xGex films to Si films are insufficient at low Ge concentration of Si1-xGex despite the high SRP value of PAA and H2O2 because the bandgap energy of Si1-xGex increase with decreasing Ge concentration.In our research, therefore, we suggested a novel oxidant, sodium periodate (NaIO4) to enhance the etch rate and the selectivity of wet etchant based on the concept of radical generation. We investigated the dependencies of Si-, Si0.7Ge0.3-film etch rate and selectivity on oxidant species, and dependencies of lateral etch rate of Si0.7Ge0.3/Si multi-stack structures on oxidant species. This was motivated by that NaIO4 generates radicals in acidic medium, such as iodyl (IO3 •) and reactive oxygen species (i.e., the superoxide radical (O2 •–) and hydroxyl (•OH) radical), as shown in Fig. 1. SRP of NaIO4 itself has relatively low (~1.60 eV) compared to PAA (~1.75 eV), IO3 •, O2 •– and •OH radicals generated from NaIO4 have higher SRP (O2 •–: ~2.80 eV and •OH: ~2.42 eV), which resulted in a higher etch rate at lower Ge concentration less than 30%.For the experiments, the Si0.7Ge0.3 layer grown on Si and 3-layer Si0.7Ge0.3/Si multi-stack wafers were grown by using ultra-high-vacuum chemical vapor deposition (EUREKA, JUSUNG ENGINEERING). Coupon wafers with 1.5 × 1.5 cm2 of Si0.7Ge0.3 and Si substrate (reference group), and patterned wafers of 3-layer Si0.7Ge0.3/Si multi-stack layers with a line width of 10 μm were prepared and then all samples were dipped in the etchant solutions for 1 min at room temperature. The thickness of the samples was characterized by using spectroscopic ellipsometry (V-VASE, J.A. Woollam). In addition, after etching of the 3-layer Si0.7Ge0.3/Si multi-stack structures, a lateral etch rate were characterized by using field-emissive scanning electron microscope (Helios 5 CX, Thermofisher).It was confirmed that our novel etchant using NaIO4 as an oxidant demonstrated extremely high etch rate for Si0.7Ge0.3 film (140 nm/min), whereas conventional etchant using oxidant PAA and H2O2 demonstrated the etch rate of 5.7 and 2.4 nm/min respectively. In addition, the selectivity between the Si0.7Ge0.3- and Si films etched by using the NaIO4 oxidant was much higher (318:1) than that etched by PAA and H2O2 oxidant (29:1 and 6:1), as shown in Fig. 2, which sufficiently satisfied the requirement of etch rate (>30nm/min) and selectivity (300:1) for fabricating GAAFETs. The lateral etch rate of 3-layer Si0.7Ge0.3/Si multi-stack, mechanism on radical generation of NaIO4, and the characterization method to quantify radicals will be presented in detail. Acknowledgement This work was supported by the Technology Innovation Program (20022467, Development of Wet Etchant and Core Materials for Next Generation Semiconductor Manufacturing Process below 10 nm) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) Figure 1

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Nanosheet (NS) gate-all-around (GAA) devices have demonstrated advantages in device performance and area scaling over finFET devices [1-11]. Enablement and future scaling of GAA devices require robust etch processes for Inner Spacer (IS) and Channel Release (CR) for well-controlled device performance and yield (Fig. 1). CR requires an isotropic, complete etch of the sacrificial SiGe layer with extremely high selectivity to the spacer (Sp0), IS, and Si channels. Furthermore, during CR, the Si channels must be released simultaneously for all sheet widths (WNS) [1], which range from 20nm to 100nm, necessitating significant over-etch (OE) on the narrowest sheets. We demonstrated excellent device performance across all WNS with more than 150 % OE on the widest sheets [1]. However, this extreme OE makes the pFET source/drain (S/D) SiGe:B especially vulnerable to damage. In this paper, we explore several mechanisms that result in SiGe:B S/D damage and demonstrate how to prevent the damage with IS, CR, and S/D epitaxial optimization.The S/D Si:B and Si:P used in our high-performance test devices are not susceptible to damage during CR due to high etch selectivity [2]. Thus, SiGe:B S/D is required to evaluate the mechanisms causing S/D damage. To enable these studies, we developed high-quality S/D SiGe:B, which shows substantial device performance improvement over our baseline S/D Si:B, with 150% increase in peak mobility, 50% reduction in Vt, and 45% reduction in Ron (Fig. 2).The ability to target IS thickness allows tuning of device performance through Cov and Ron and is critical for future device scaling. In addition, the IS plays a critical role as a physical barrier to prevent S/D damage during CR [1,2]; reducing IS thickness below a critical value can result in S/D damage. The optimal IS thickness is determined by balancing maximum device performance for all WNS while maintaining S/D integrity during CR. This process window can be maximized by optimizing the CR etch process, and can be further increased by integrating an Si:B buffer in the S/D epitaxy. We have developed four CR processes with different chemistries and evaluated their process windows.We evaluated S/D damage for two CR processes versus IS thickness. We observed no S/D damage with Process A until 4nm IS thickness at 50% OE (Fig. 3a). Process C showed no damage at 4nm IS thickness, even up to 100% OE. The plan-view TEM in Fig. 3a shows that S/D damage occurs at the corners of the S/D region as well as at the center, indicating several mechanisms for S/D damage (see Fig. 4): CR etch gas permeation through the IS, exposed S/D through pinholes in the IS or at the IS edges due to rounded IS shape, and exposed S/D at the intersection of the Si/SiGe fins and gate.To isolate and characterize permeation of the CR etch gas through the IS, we deposited various thicknesses of IS on SiGe/Si multilayers (Fig. 5a), then exposed the structures to CR Process A. The SiGe layers showed no damage until the IS layer was thinned to <1nm. The difference in critical thickness for etch gas permeation on fully integrated structures compared to these test structures (4nm compared to <1nm) could be attributed to the other mechanisms.S/D damage due to IS permeation can be prevented by a better quality IS; by optimizing the CR chemistry to tune the selectivity between the sacrificial SiGe and the S/D SiGe:B (Fig. 5b); or by integrating a Si:B buffer prior to S/D SiGe:B deposition (Fig. 6). The process window then can be maximized by selecting the best CR process since selectivity to Si:B and permeation through the IS varies with the chemistry. Fig. 7 shows the improvement in the process window with a 2nm Si:B buffer on wafers with no IS for Processes A, B and C.The other S/D damage mechanisms highlighted in Fig. 4 are characterized in Fig. 3b. The S/D damage starts at the corners of the active region and the extent of damage increases with CR OE. These failure modes require changes in integration to improve the Sp0 at the fin-gate corner, reducing the IS rounding, or creating a straighter etch front across the sheet [2].S/D damage during CR is a significant issue in NS architecture. This can be mitigated by optimizing the CR etch process, incorporating an Si:B buffer layer, improving the IS quality or shape, and improved integration. Understanding these mechanisms is critical to ensure robust S/D quality with scaling for future technology nodes. Figure 1

Alkali Wet Chemicals for Ru with Advanced Semiconductor Technology Nodes

Wet chemicals for ruthenium (Ru) etching are required for the formation of reliable Ru interconnects in advanced semiconductor technology nodes. In the present study, a novel alkali wet etchant, referred to as TK-1, has been developed in order to overcome issues with conventional Ru etchants, such as a low etch rate and the formation of toxic RuO4 gas. Regardless of the Ru deposition process, TK-1 exhibits a high Ru etching selectivity of greater than 100 relative to dielectric and liner materials. It also suppresses the production of RuO4 during the etching process. TK-1 has potential applications for Ru recess etching during fully self-aligned via fabrication.

Vapor‐Phase Infiltrated Organic–Inorganic Positive‐Tone Hybrid Photoresist for Extreme UV Lithography

AbstractContinuing extreme downscaling of semiconductor devices, essential for high performance and energy efficiency of future microelectronics, hinges on extreme ultraviolet lithography (EUVL) and addressing associated challenges. One of such challenges is a need for improved EUV photoresists featuring simultaneously high sensitivity, resolution, and etch selectivity. Here, a new, positive‐tone, organic–inorganic hybrid EUV photoresist is demonstrated that delivers a high‐resolution EUVL and electron‐beam lithography (EBL) patterning capability combined with high sensitivity and etch resistance. The new resist, poly(methyl methacrylate) infiltrated with indium oxide (PMMA‐InOx), is synthesized via vapor‐phase infiltration (VPI), a material hybridization technique derived from atomic layer deposition. The weak binding of the gaseous indium precursor, trimethylindium, to the carbonyl group in PMMA allows the synthesis of hybrids with inorganic content distributed uniformly in the resist, enabling high EUVL and EBL sensitivities (18 mJ cm−2 and 300 µC cm−2, respectively) and high‐resolution positive‐tone EUVL patterning (e.g., 40 nm half‐pitch line‐space and 50 nm diameter contact hole patterns) with high Si etch selectivity (&gt;30–40). The low exposure doses required to pattern the PMMA‐InOx hybrid resist, high etch resistance, and processing strategies, which are developed, can pave the way for using infiltration‐synthesized hybrid thin films as reliable positive‐tone EUV photoresists for future semiconductor patterning.

Die-embedded packaging using Corning® multi-layered glass

Die-embedded (DE) packaging technologies in recent years have ventured into advanced packaging structures, such as fan-out wafer level packages (FOWLPs) or package-on-packages (PoPs). They offer higher density at lower costs, despite many challenges, such as the die-shift and warpage problems often observed during the molding process, caused by the high shrinkage and high coefficients of thermal expansion (CTEs) of the molding materials. This in turn makes it difficult to accurately mount the high-density fine-pitch bumps and adversely affects the overall yield, especially in processes using large-size substrates. Glass, known for its superior dimensional and thermal stability and its low or tunable CTEs, can be advantageous in reducing die-shift and warpages as opposed to other alternative material solutions for the molding process. In this paper, we propose a packaging solution based on a glass substrate incorporating a plurality of precisely dimensioned cavities, with a chip positioned in each cavity to prevent them from shifting during processing. Corning® Adaptive Formed Glass (AFG), a laminate glass with a unique clad/core/clad structure, allows for effectively forming cavities with high dimensional precision and positional accuracies as well as surface flatness through a wet etch process. Using a 0.5mm thick laminate Corning® AFG glass, we successfully designed and fabricated three types of DE packages with lab scale tools at Korea Electronics Technology Institute (KETI): single- and double-sided DE packages, and package-on-packages (POPs). High etching selectivity over 20:1, which was achieved by carefully designing the core and clad glass compositions, enabled a wet-etch cavity forming process with accurate cavity depths and flat bottom surfaces (&lt; ± 2.5μm) with relative ease. A double-sided DE package with a total thickness of 600μm was fabricated with two 125μm-thick IC chips, one embedded on each side of the substrate, and connected by metallized through glass vias (TGVs). A POP measured at 5.1×5.1×1.27 mm3 was also successfully demonstrated by using two built-in double-sided DE packages joined by flip-chip bonding, equivalent to stacking four layers of conventional single-sided DE packages. The double-sided DE packages and POPs presented in this paper are believed to be the world’s first demonstration on glass. The work also manifests the immense potential of Corning® AFG glass in enabling higher density IC packaging and large-size panel-level (or wafer-level) packaging.

Highly selective isotropic gas-phase etching of SiO2 using HF and methanol at temperatures –30 °C and lower

The gas-phase etching of SiO2 was examined using HF and methanol vapor at temperatures below 0 °C and at low pressure. The etching rate of SiO2 increased with decreasing temperature and showed a maximum around –30 °C. The obtained etching rate was a maximum of 40 nm min−1 at plasma-enhanced chemical vapor deposition SiO2. The etching rate of SiN examined for comparison was more than ten times smaller than that of SiO2 under the same condition. As a result, the etching selectivity of SiO2 to SiN was found to be over 20 at –40 °C. When utilizing a low temperature of less than –30 °C, gas-phase etching of SiO2 showing a high etching rate and selectivity was achieved.

Fused silica microchannel fabrication with smooth surface and high etching selectivity

Channel fabrication technology has become increasingly important for microfluidic and nanofluidic devices. In particular, glass channels have high chemical and physical stability, high optical transparency, and ease of surface modification, so that there is increasing interest in glass microfluidic devices for chemical experiments in microfluidics and nanofluidics. For the fabrication of glass channels, especially those with a high aspect ratio (depth/width), lithography using a metal resist and dry etching have mainly been used. However, there are still issues involving the surface roughness of the etched channel and the low etching selectivity. In this study, a microchannel fabrication method with high etching selectivity that produces a smooth etched surface was developed. First, interference during dry etching by remaining Cr particles after the photolithography and Cr etching processes was assumed as the cause of the rough etched surface. Three different dry etching processes were introduced to verify this. In process 1 without removal of the Cr particles, the etched surface was not flat and had a 1 μm scale roughness. In process 2 where a cleaning process was included and high power etching was conducted, a smooth surface with a 1 nm scale roughness and a faster etching rate of 0.3 μm min−1 were obtained. For this high-power etching condition, the etching selectivity (fused silica/Cr) was relatively low at approximately 39–43. In process 3 with a cleaning process and low-power etching, although the etching rate was relatively low at 0.1 μm min−1, a smooth surface with 1 nm scale roughness (10 nm scale roughness deeper than 40 μm in the depth region) and a much higher etching selectivity of approximately 79–84 were obtained. The dry etching method presented in this study represents a significant contribution to microfluidics/nanofluidics for microchannel/nanochannel fabrication.

Anisotropic Etching of InGaN Thin Films with Photoelectrochemical Etching to Form Quantum Dots

Traditional methods for synthesizing InGaN quantum dots (QDs), such as the Stranski-Krastanov growth, often result in QD ensembles with low density and non-uniform size distribution. To overcome these challenges, forming QDs using photoelectrochemical (PEC) etching with coherent light has been developed. Anisotropic etching of InGaN thin films is demonstrated here with PEC etching. InGaN films are etched in dilute H2SO4 and exposed to a pulsed 445 nm laser with a 100 mW/cm2 average power density. Two potentials (0.4 V or 0.9 V) measured with respect to an AgCl|Ag reference electrode are applied during PEC etching, resulting in different QDs. Atomic force microscope images show that while the QD density and sizes are similar for both applied potentials, the heights are more uniform and match the initial InGaN thickness at the lower applied potential. Schrodinger-Poisson simulations show that polarization-induced fields in the thin InGaN layer prevent positively charged carriers (holes) from arriving at the c-plane surface. These fields are mitigated in the less polar planes resulting in high etch selectivity for the different planes. The higher applied potential overcomes the polarization fields and breaks the anisotropic etching.

Atomic layer etching of Sn by surface modification with H and Cl radicals

Sn is the one of the materials that can be used for next generation extreme ultraviolet (EUV) mask material having a high absorption coefficient and, for the fabrication of the next generation EUV mask, a precise etching of Sn is required. In this study, the atomic layer etching (ALE) process was performed for the precise etch thickness control and low damage etching of Sn by the formation SnHxCly compounds on the Sn surface using with H and Cl radicals during the adsorption step and by the removal of the compound using Ar+ ions with a controlled energy during the desorption step. Through this process, optimized ALE conditions with different H/Cl radical combinations that can etch Sn at ∼2.6 Å cycle−1 were identified with a high etch selectivity over Ru which can be used as the capping layer of the EUV mask. In addition, it was confirmed that not only the Sn but also Ru showed almost no physical and chemical damage during the Sn ALE process.

Selective atomic layer etching of Al2O3, AlNx and HfO2 in conventional ICP etching tool

The atomic layer etching process of Al2O3, AlNx and HfO2 in conventional plasma etching tool was investigated. The etching process is based on surface modification by fluorocarbon film deposition from Ar/CF4/H2 plasma and subsequent activation of etching by Ar ion bombardment from plasma. The study of deposition process showed that varying plasma composition surface kinetics significantly change from deposition to etching. This is associated with the rise of fluorine concentration both in plasma and in deposited fluorocarbon film. Plasma mixture with low CF4 fraction was chosen for modification step of ALE process because it provides low fluorinated film which does not etch SiO2 and TiN improving selectivity to the potential mask material in etch process. The ALE process shows self-limiting characteristics providing the ALE process window at duration of modification step. The etch rate is 0.16 nm/cycle for Al2O3, 0.20 nm/cycle for AlNx and 0.11 nm/cycle for HfO2, which is close to monolayer mode. Relatively short cycle duration provides feasible etch rate in terms of time consumption. The significant selectivity over TiN (more than 20) was achieved allowing employing TiN as mask material for high resolution selective etching.

(Digital Presentation) Selective SiGe Vapor Etching Using Br2 in View of Nanosheet Device Isolation

Forksheet transistors are lateral nanosheet devices with a forked gate structure [1,2]. The physical separation of N- and PFETs by a dielectric wall enables N-P space scaling and consequently sheet width maximization within the limited footprint of low-track-height standard cells. Bottom dielectric isolation has been proposed to circumvent the junction isolation trade-off between punch-through suppression on the one hand and junction leakage and capacitance on the other hand [3]. A typical fabrication scheme includes the epitaxial growth of Si/Si1-yGey/multi-{Si1-xGex/Si} epi stacks (y>x) where the bottom Si1-yGey layer is later replaced by a SiN/SiCO isolation [4]. The fabrication scheme relies on selective etching of the sacrificial Si1-yGey layer with respect to the {Si1-xGex/Si} multi-stack. Owing to the very small dimensions (e.g. sub-10 nm nanowire channel diameter), high etch selectivity towards both Si1-xGex and Si, and excellent process controls are mandatory. This sets stringent requirements on the epitaxial stacks (thicknesses and composition control, sharpness of interfaces, and absence of strain relaxation) [4] as well as on the etch process itself (high selectivity, limited Si1-xGex and Si consumption) [5-7].The selective Si1-yGey removal requires a great precision in its adjustment, with the risk of experiencing process variabilities and yield issues. Selective SiGe etching is typically done in advanced wet or dry chemistries and is sensitive to both strain in and oxidation of individual layers [4-6]. Also, HCl-based vapor etching has been reported for SiGe removal, with high selectivity towards Si [7]. The HCl vapor etching requires a sufficiently high process temperature (typically ≥ 600°C). This makes it less attractive for fabrication schemes with bottom isolations. The presence of the Ge-rich Si1-yGey layer in the as-grown epi stack results in an enhanced risk for unwanted layer relaxation.A low temperature Br2-based vapor etching process is proposed as an alternative for the selective Si1-yGey removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etch selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x=0.2, 0.23, and 0.3).Figure 1 compares the etching characteristics of HCl, HBr, and Br2 as obtained for blanket Si1-xGex layers where the Ge content was varied between 0.2 and 0.5. In all cases, the etching is kinetically controlled. The etching rates indeed show a clear exponential dependence as function of the process temperature. While the etching rates are similar for HCl and HBr, the Arrhenius plot is shifted to ~300°C lower temperatures for Si1-xGex etching with Br2. For each process gas, the etching rate increases with increasing Ge concentration. This difference in etching rate as function of layer composition is highest for Br2. Figure 2 reports the obtained etching selectivity between Si0.5Ge0.5 and Si1-xGex (x = 0.15 – 0.36) as obtained for Br2 etching on blanket wafers. Selective etch tests with Br2 as etching gas were conducted on fin patterned structures consisting of Si-substrate / 10 nm Si0.5Ge0.5 / 3x {9 nm Si1-xGex / 9 nm Si}. Different etching times have been applied to demonstrate the concept and to validate etch selectivity between Si0.5Ge0.5 and Si1-xGex/Si. Figure 3 displays low magnification X-TEM images of the structure with x=0.2, after fin patterning, 1 min, and 3 min Br2 etching. The selective etching of the Si0.5Ge0.5 layer is clearly demonstrated, although the shortest etching time is not sufficient for complete Si0.5Ge0.5 removal while the sample etched for 3 min was clearly over etched. Lateral material loss of the upper two Si0.8Ge0.2 layers is limited to 2-3 nm (Fig. 3b) and 3-4 nm (Fig. 3c), respectively. During lateral Si0.5Ge0.5 etching, the lowest Si0.8Ge0.2 layer gets exposed to the Br2 etching gas both from the side walls as well as from the bottom surface. The severe etching of this layer is also observed for other etching routines and can easily be avoided by adding a thin Si layer between the Si0.5Ge0.5 layer and the first Si0.8Ge0.2 layer.

(Digital Presentation) Selective SiGe Vapor Etching Using Br2 in View of Nanosheet Device Isolation

Both forksheet and CFET device layouts contain local dielectric isolation layers to circumvent junction isolation trade-offs which are specific for these designs. Typical fabrication schemes start with the epitaxial growth of complicated SiGe/Si multi stacks with at least two different Ge concentrations where a Ge-rich SiGe layer is later replaced by an isolating dielectric. This work proposes a low temperature Br2-based vapor etching process as an option for the selective SiGe removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etching selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x = 0.2 - 0.3).

Thermal-cyclic atomic layer etching of cobalt with smooth etched surface by plasma oxidation and organometallization

Thermal-cyclic atomic layer etching of a Co film and a fine pattern with a smooth etched surface by plasma oxidation and organometallization is demonstrated. One cycle of the etching process consists of a two-temperature process. In the first step, plasma oxidation of Co is carried out at a low temperature of 25 °C to obtain a smooth Co oxide layer. In the second step, the Co oxide is organometallized with acetylacetone and desorbs at a high temperature of 210 °C that is suitable for organometallization and desorption. The etched amount per cycle is 0.6 nm, which is the same as the saturation amount of oxidation. A smooth etched surface is obtained after 20 cycles with a root mean square roughness of 0.53 nm, which is only slightly higher than the initial value of 0.34 nm. High etching selectivity over barrier metal of titanium-nitride was obtained. The two-step temperature cycle is crucial to achieve favorable etching with smooth etched surfaces.

Chromium oxide – A novel sacrificial layer material for MEMS/NEMS and micro/nanofluidic device fabrication

Free standing membranes for fluidic devices typically require long etching times due to the slow, diffusion limited exchange of etchant and etch products when large etch distances are involved. In these cases, high etch selectivity is required between the sacrificial and channel-wall materials. Here, we introduce chromium oxide, Cr2O3, as a versatile sacrificial layer material for the fabrication of microfluidic and nanofluidic channels. Chromium oxide has many desirable attributes as a sacrificial layer: it can be deposited by sputtering to form stress-controlled films, it adheres well to both metal and dielectric surfaces, it is resistant to most acids and bases, but etches rapidly in standard chromium etchants, and has minimal tendencies to react with other commonly used materials. In addition, typical chromium etchants are highly selective to materials commonly used in microfabricated systems. To fully explore the process characteristics of this material we performed a comprehensive set of experiments to quantify its behavior in ways relevant to its use in device fabrication. The results presented in this paper will provide a starting point to optimize Cr2O3 for fabrication of fluidic devices.

Study of Etch Stop Layer on Characteristics of Amorphous Aluminum Oxide Thin Film

To protect the active layer, which are inter layer dielectrics (ILD) and metal lines, from being damaged by UV laser during the etching process, etch stop layers (ESL) are used in patterning process of the integrated circuits (ICs) fabrication in back end of line (BEOL). The ESL material should have a higher etch selectivity than the active layer. Therefore, it must have a low dielectric constant and high chemical resistance. Aluminum oxide compounds (AlOx, AlOC, AlON, etc.) are highly suitable for use as ESL due to the low dielectric constant between about 4 and 9, high etch selectivity, high density (2.5-3.8 g/cm3) and pattern transfer capability. We focused on lowering the dielectric permittivity and increasing the density by controlling the precursor/reactant pulsed time of atomic layer deposition (ALD).

Etch Characteristics of Low-K Materials Using CF3I/C4F8/Ar/O2 Inductively Coupled Plasmas

In this study, pulsed CF3I/C4F8/Ar/O2 inductively coupled plasmas have been studied for low-k etching, and the effects of CF3I addition to C4F8/Ar/O2 on the plasma characteristics and etch characteristics of low-k materials were investigated. The increased ratio of CF3I/(CF3I+C4F8) in the gas mixture increased CF3 radicals while decreasing CF2 radicals in the plasma, and which are related to the etching and polymerization, respectively. Therefore, the etch rates of SiCOH increased with increasing the CF3I ratio. However, the etch selectivity over an amorphous carbon layer and photoresist was the highest at the ratio of 0.5 because the CF2/F flux ratio from the plasma and the C/F ratio on the polymer layer were the highest at the CF3I ratio of 0.5. The SiCOH damage was decreased with increasing CF3I ratio and the SiCOH damage appeared to be very low, particularly when the CF3I ratio was ≥0.5 by showing low Si–CH3 bond loss, low F penetration, and a low surface roughness. Therefore, it is believed that, as opposed to the C4F8/Ar/O2 gas mixture only, mixing 50% CF3I into the C4F8/Ar/O2 gas mixtures resulted in not only a high etch selectivity over mask materials, but also a potentially reduced etch damage.

Ge−Sb Thin Films Patterned by Heat‐Mode Lithography

A binary Te‐free phase‐change material Ge9.15Sb90.85 (GS) is investigated as the heat‐mode resist. A high etching selectivity ratio can be achieved by matching a suitable developer. A reasonable explanation for the positive development is proposed based on the chemical binding energy analysis. High‐resolution relief patterns are fabricated on the GS films by laser direct writing and wet etching. It reveals that GS is a promising heat‐mode resist for the fabrication of photonic devices.