High Etch Selectivity Research Articles

Finfet Gate Etch Towards 16nm Node CMOS Technology

The 3D tri-gate FinFET device architecture is a key transistor scaling to 22nm node and beyond for its excellent short-channel performance[1]. However, compared with planar transistors, it poses greater challenge in the finFET gate etch.[2] As shown in fig.1, the etch needs to stop on top of the fin while etching further down to the STI oxide layer. Therefore, the top of fin needs to endure long time over etch without any structural damage which would adversely affect device performance. What’s more, the gate profile must be vertical and there should not be residual in the corner of gate and fin. It is not an easy task to achieve, at the same time, the three goals of vertical gate profile, no residual in the corner of fin and gate, as well as no structure damage on the top of fin, due to an unavoidable tradeoff. More specifically, vertical gate profile and no residual in the corner of fin demand strong etch function and light polymer, while no structure damage in the top of fin requires weak etch function and heavy polymer, which points to high etch selectivity of silicon to oxide layer.To achieve good etch results, one often falls into this dilemma. As far as we know, few publicly available papers have provided satisfactory solutions to the above- mentioned problem. In this work, we deal with it.The process of gate stack with CD below 30nm is illustrated in fig.2. Then, a HBr/O2 process in transformer coupled plasma is applied to finFET gate etch. As shown in fig.3, gate profile is vertical, fin is well protected and no residual appears in the corner fin.In conclusion, an HBr/O2 plasma etch process of finFET gate with CD below 30nm is investigated.Through appropriate tradeoff , an etch result of vertical gate profile, no residual in the sidewall and corner of fin, no structure damage on the top of fin is achieved.

Progresses in cMUT device fabrication using low temperature processes

In this paper, we present an original fabrication process of capacitive micromachined ultrasonic transducers (cMUTs) using a low temperature method for high frequency medical imaging applications. The process, which is limited to 400 °C, is based on surface micromachining. The material choices are adapted in order to respect the thermal specifications allowing monolithic integration. Thus, we have found alternative methods to replace the usual high temperature steps in cMUT elaboration. In this way, a nickel silicide layer, presenting good physical and electrical characteristics, is used as a bottom electrode. The membrane, silicon nitride, is deposited using a 200 °C PECVD process. Then, a metallic layer is chosen as a sacrificial layer, in order to achieve the cavity. For that, nickel has been chosen due to its low roughness and its high etching selectivity during the excavation. After their fabrication, the transducers have been tested to verify their functionality and, thus, to validate this low temperature process. Device physical properties have been determined by electrical and optical measurement in air. We evaluated resonance frequency, collapse voltage and electromechanical coupling coefficient in accordance with the simulation. Eventually, low charging effects and low initial deflections can predict good long-term use and ageing of the cMUTs.

A Study of Self-Aligned-Via Based All-in-One Etch

Trench-first-metal-hard-mask (TFMHM) approach has been widely utilized together with punch-through-via (PTV) scheme for copper interconnect formation since sub-65nm CMOS technology node. In this work, compared to the traditional PTV scheme on sub-45nm test vehicle, we successfully demonstrate that the self-aligned-via (SAV) based all-in-one (AIO) etch process could be fulfilled on thin metal hard-mask and is capable of delivering much better via related TDDB performance without the performance degradation of electromigration (EM), while the contact resistance (Rc) exists different trend with PTV scheme. The high etch selectivity is imperative in both partial via etch, trench etch and liner removal step to reduce the via encroachment on metal hard-mask, the via CD along the unconfined (metal hard-mask) direction should be also optimized to achieve the above desired performance without tiger teeth beneath via bottom. Both via and trench etch recipe need be well optimized to deal with etch stop, via bottom grass and polymer residue issues. Besides, SAV delivers much good yield performance even at misalignment via chain test key, which indicates its very robust overlay margin. But it suffers yield loss at some sub-rule test structure in which trench line end CD is strictly confined by nearby pattern.

Complex Film Stack Etch Application for BSI CIS in Mesa Etcher

For most people, Apple’s introduction of backside-illuminated (BSI) CMOS image sensors (CIS) in their iPhone4 may have been the first time they became aware of this technology. Compared with traditional front-illuminated CMOS, light in a BSI CIS can strike the photocathode directly without passing through wiring layer. Thus, photon absorption efficiency increases from 60% to 90%. As the size of the CIS decreases, this performance improves. Now, BSI CIS are widely used in digital cameras, smartphones, etc. However, placing the active matrix transistors behind the photocathode gave rise to a host of new problems, such as cross-talk, which would cause noise and dark-current, and color mixing between adjacent pixels. Solving these problems calls for a low-cost solution in the etch process used in volume production. Etching a BSI CIS film stack is very complex. The etch must pass through approximately half a micron of silicon oxide or nitride, a high-k film and more than 2 microns of silicon. As many of the pre-layers have been planarized, the thickness of oxide/nitride film or silicon film is very variable (typically more than 10%). High etch selectivity and precise time control are therefore necessary. The Applied Materials Centura® AdvantEdge™ Mesa™ etch chamber maintains a high silicon etch rate while preserving a vertical sidewall profile. The oxide/nitride etch rate was acceptable; it also exhibited high selectivity and minimal micro-loading. This chamber was therefore the best choice for this application. The EyeD® endpoint system was used to monitor the interface of the film to control process time. The backside grounding layer (application 1) is similar to pad1. To eliminate deposition voids, a very tapered profile was required (70º+/-5°). The SF6/Cl2/C4F8 recipe could achieve that profile, but had very high silicon etch rate. It would create serious sub-trench issues when the high-k layer was punched through. Its process window was also very marginal. CF4/CHF3 was tested as an alternative, but produced excessive polymer deposition. The profile of high-k became unacceptably tapered. We ultimately used a two-step approach to precisely control polymer deposition and this approach produced a very good profile. For the backside interconnection layer (application 2), tapered profiles were also required. More importantly, the etch had to pass through more than 2 microns of silicon while retaining an approximately 70° profile angle. The gas ratio had to be precise, and pressure was kept at a mid-level. The final profile, which was very good, was superior to that achieved by our competitors. The silicon thickness is very variable because of the limitations of the planarization process. For best production flexibility, we use the EyeD optical endpoint system. Initially, the signal was very weak when the process was deep in the silicon. However, a very robust endpoint was obtained by fine-tuning the EyeD algorithm.

Attempts to form the 10-nm-order pitch of self-assembled nanodots using PS-PDMS block copolymer

Block copolymer (BCP) self-assembly exhibits its ability to form various nanostructures with a size down to 3 nm, which is particularly attractive for emerging technologies such as bit patterned media (BPM). Poly(styrene-b-dimethyl siloxane) (PS-PDMS) has been acknowledged as the most promising block copolymer for self-assembly fabrication due to its possibility to form nanopattern with a fine pitch, high etching selectivity, and its characteristic of robustness for pattern transfer. Here, we attempt to form PS-PDMS self-assembled nanodot array with a 10-nm-order pitch in order to satisfy the demand of low cost technique to form ultrahigh density nanodot array for BPM, which is regarded as the next-generation magnetic recording media, and for quantum devices such as the third-generation quantum dot photovoltaic cell and future battery cell. In this study, self-assembled nanodot array on a large area with pitches of 11 nm ( σ = 2.08 nm) and 10 nm ( σ = 1.61 nm) was formed using PS-PDMS with molecular weights of 5600–1300 g/mol (minority block volume fraction f PDMS = 19.8%) and 4700–1200 g/mol (f PDMS = 21.4%), respectively. In experiments, it was shown that some critical parameters, such as the thickness of PS-PDMS film, the treatment of the substrate surface, and annealing condition, played crucial roles in forming 10-nm-order size of self-assembled nanodot array using PS-PDMS. The relationships between pitches of PS-PDMS nanodot array and the product of the total number of segments and the Flory-Huggins segmental interaction parameter (χN) obtained by calculations and experiments will be discussed. Based on the position of PS-PDMS on mean-field phase diagram for BCP melts, the possibility to form nanodot array with a pitch of less than 10 nm is described. This study promises to open way toward the fabrication of more than 7.45 Tbit/in. 2 storage devices and the application of quantum devices.

Efficient TSV Resist and Residue Removal in 3DIC

The continuing challenge to meet the need for lighter, smaller, faster and smarter electronic systems has pushed the advancement of 2.5D and 3D technology. The ability to create and integrate through-silicon vias (TSV) into device designs in 2.5- and 3-D platforms allows a decrease in interconnection path length, which results in improved device performance and reliability in a small form factor. Mainly due to its high silicon etch rate and selectivity to mask materials, the Bosch process is often used in the TSV fabrication. In this process, the silicon via is created by the deep reactive ion etching (DRIE). DRIE is comprised of repeating a combination of steps: an etch step and a passivation step. The passivation created in the DRIE process results in a fluoropolymer residue remaining on the wafer at the end of the process. The residue must be removed to enable deposition of a defect-free barrier, which enables a defect-free seed layer and void-free plating into the via. There are numerous technical papers and presentations on the etching and filling of these vias but the process for cleaning remains under addressed. Initially, standard processes used after RIE and consisting of an ashing process to remove any remaining photoresist, followed by immersion in a solution-based post etch residue remover were adopted for post-TSV cleans. However, the fluoropolymer does not have the same chemical characteristics as typical post-RIE etch residues and the major challenge has been the difficulty to completely remove it, especially on the via sidewall, using traditional post etches residue removers. Therefore, new formulated cleaning solutions and processes are actively sought for the removal of post etch residue for TSVs. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using a proprietary environmentally friendly chemistry, coupled with a megasonic final rinse provides a unique solution for both polymer residue and photoresist removals on high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.

Damaged silicon contact layer removal using atomic layer etching for deep-nanoscale semiconductor devices

Silicon atomic layer etching (ALET) using Cl2 is applied to remove the damaged layer on a 30 nm contact silicon surface formed by high-energy reactive ions during high aspect ratio contact etching, and its effects on the damage removal characteristics are investigated. Compared to a conventional damage removal method, such as the low-power CF4 plasma treatment technique, ALET produces less secondary damage to the substrate and gives exact etch depth control and extremely high etch selectivity to the contact SiO2 insulating pattern mold. When ALET is applied after a conventional damage removal technique, the sheet resistance of the damaged contact silicon surface is improved to a level close to that of a clean silicon surface, while exact atomic-scale depth control is maintained without changes in the pattern mold profile.

Investigations on a Multiple Mask Technique to Depress Processing-Induced Damage of ICP-Etched HgCdTe Trenches

A multiple mask technique, integrating patterned silicon dioxide (SiO2) film over patterned thick photoresist (PR) film, has been investigated as a method to perform mesa etching for device delineation and electrical isolation of mercury cadmium telluride (HgCdTe) third-generation infrared focal-plane arrays. The multiple mask technique was achieved by standard thick PR photolithography, SiO2 film deposition to cover the thick PR patterned film, and etching the SiO2 film at the bottom region after another photolithography process. The dynamic resistance in the zero-bias and low-reverse-bias regions of HgCdTe photodiode arrays isolated by inductively coupled plasma (ICP) etching with the multiple mask of patterned SiO2 and patterned thick PR film underneath was improved one- to twofold compared with a simple mask of patterned SiO2. It is suggested that the multiple mask technique is capable of maintaining high etching selectivity while reducing the side-wall processing-induced damage of ICP-etched HgCdTe trenches. The results show that the multiple mask technique is readily available and shows great promise for etching HgCdTe mesa arrays.

Investigations of AlGaN/GaN HFETs utilizing post-metallization etching by nitric acid treatment

This work investigates AlGaN/GaN heterostructure field-effect transistors (HFETs) processed by using a simple post-metallization etching (PME) treatment. Decreased gate length (LG) can be achieved by using nitric acid (HNO3) PME treatment owing to the high etching selectivity of HNO3 of Ni against the Au and GaN layer. Influences on LG, etched gate profiles and device characteristics with respect to different PME processing parameters by HNO3 treatment are systematically investigated. Optimum device performance is obtained as LG was reduced to 0.5 µm by using a 1 µm long gate mask by immersing the device into a 45% diluted HNO3 solution for 35 s. Improved device performances, including maximum drain–source current density (IDS, max: 657.6 mA mm−1 → 898.5 mA mm−1), drain–source saturation current density at zero gate bias (IDSS0: 448.3 mA mm−1 → 653.4 mA mm−1), maximum extrinsic transconductance (gm, max: 158.3 mS mm−1 → 219.2 mS mm−1), unity-gain cut-off frequency (fT: 12.35 GHz → 22.05 GHz), maximum oscillation frequency (fmax: 17.55 GHz → 29.4 GHz) and power-added efficiency (P.A.E.: 26.3% → 34.5%) compared to the untreated reference device, have been successfully achieved.

Extreme ultraviolet lithography mask etch study and overview

An overview of extreme ultraviolet lithography (EUVL) mask etch is presented and a EUVL mask etch study was carried out. Today, EUVL implementation has three critical challenges that hinder its adoption: extreme ultraviolet (EUV) source power, resist resolution- line width roughness-sensitivity, and a qualified EUVL mask. The EUVL mask defect challenges result from defects generated during blank prepa- ration, absorber and multilayer deposition processes, as well as pattern- ing, etching and wet clean processes. Stringent control on several performance criteria including critical dimension (CD) uniformity, etch bias, micro-loading, profile control, defect control, and high etch selectivity requirement to capping layer is required during the resist pattern duplica- tion on the underlying absorber layer. EUVL mask absorbers comprise of mainly tantalum-based materials rather than chrome- or MoSi-based materials used in standard optical masks. Compared to the conventional chrome-based absorbers and phase shift materials, tantalum-based absorbers need high ion energy to obtain moderate etch rates. However, high ion energy may lower resist selectivity, and could introduce defects. Current EUVL mask consists of an anti-reflective layer on top of the bulk absorber. Recent studies indicate that a native oxide layer would suffice as an anti-reflective coating layer during the electron beam inspec- tion. The absorber thickness and the material properties are optimized based on optical density targets for the mask as well as electromagnetic field effects and optics requirements of the patterning tools. EUVL mask etch processes are modified according to the structure of the absorber, its material, and thickness. However, etch product volatility is the fundamen- tal requirement. Overlapping lithographic exposure near chip border may require etching through the multilayer, resulting in challenges in profile control and etch selectivity. Optical proximity correction is applied to fur- ther enhance the resolution. Other resolution enhancement techniques, such as phase shifting, are also in consideration for EUVL. Phase-shifting will involve partial etching of the multilayer. The trend to use shorter EUV wavelength (e.g., 6.7 nm) for enhancing resolution will use new multilayer and absorber compositions, and will require new etch process develop- ment efforts. TaBO/TaBN absorber layers (features down to 40 nm) were etched with vertical profiles, low etch CD bias, and 1.7 nm etch CD uniformity (3σ). In the light shed application, Mo∕Si multilayer etching yielded vertical profiles and high etch selectivity. © 2013 Society of Photo-Optical

Evolution of Dual-Layer Patterning Film for Lithography Applications

As the IC industry progresses through each technology node on the ITRS roadmap to continually produce increasingly high performance devices, new processes are required to realize the high yields necessary for success. We present and review the evolution of patterning film applications, and recent developments in the anti-reflective coating (ARC) and advanced patterning film (APF) processes. Characteristics of dual-layer patterning film combination to achieve high etch selectivity and good process integration are also discussed.

A Study on the Fabrication of Nanostructures with High Aspect Ratio and Large Area Uniformity

Nanoimprint lithography (NIL), as a promising next generation lithography method, has the advantages of high throughput, sub-10-nm feature and low cost. However, the requirements, such as the structure with high aspect ratio, large area uniformity, and pattern transfer on nonflat surface, have barely been satisfied at the same time. In this study, the authors present a novel fabrication process by introducing a three-mask-layer (TML) Soft UV NIL technique which proves to be a simple and effective method. The initial mold with low aspect ratio can guarantee the imprint uniformity on large area under a high pressure in NIL. Meanwhile, high aspect ratio structure can be easily obtained due to a high etching selectivity of SiO2 to resist in O2 plasma dry etching. Using the proposed technique to fabricate 40 nm gratings with the aspect ratio as high as 6 is proved successful. Uniform photonic crystal (PC) structures with micrometer scale nonflat steps are obtained on large area. The photoluminescence enhancements of the PC light-emitting diode (LED) fabricated by the proposed method to the one with conventional process and un-patterned LED are 1.6 fold and 2.2 fold, respectively.

Thin Film Block Copolymer Assembly in Mixtures of Highly Selective Solvents

Perpendicular orientation of block copolymer (BCP) domains in thin films is generally preferred over parallel orientation for lithographic applications. [1] Thermal annealing can be used to promote this orientation, but often requires a top coat since one block will typically wet the air interface. [2] Solvent annealing is an attractive alternative for achieving perpendicular orientation of the domains by neutralizing the surface energy of the air interface. Many examples of using solvent annealing in BCP thin films exist in the literature, involving domain non-selective [3] and selective [4] solvents. Silicon-containing polymers are desirable for lithographic applications because their high chi-parameters and high etch selectivity allow them to self-assemble into small domains and be transferred easily into an underlying substrate by oxygen etching. [5,6] This paper describes the process used to solvent anneal a new silicon-containing polymer, poly(trimethylsilyl styrene-b-lactide) (PTMSS-b-PLA) using cyclohexane vapor, a solvent that preferentially swells the PTMSS domain.

Fabrication of DLC-Based Micro-Gear Patterns by Room-Temperature Curing Nanoimprint Lithography Using Glass-Like Carbon Molds

ABSTRACTThe fabrication of diamond-like carbon (DLC) micro-gear by room temperature curing nanoimprint lithography (RTC-NIL) using glass-like carbon (GC) molds as applications to the DLC-based medical MEMS (Micro Electronic Mechanical Systems) was investigated. The DLC film which has excellent properties similar to chemical vapor deposited (CVD) diamond films was used as the patterning material. We propose GC as mold material because GC has higher etching selectivity than a diamond film. The etching selectivity of polysiloxane film against a GC substrate is about 5 times as high as that of a diamond film. Therefore we fabricated the GC molds that have micro-gear patterns with 30 µm-tip diameter and 500 nm-tooth thickness. We carried out the RTC-NIL process using the GC micro-gear molds under the following optimum conditions. 1 min-time from spin-coating to imprint: t1, 0.5 MPa-imprinting pressure: P and 5 min-holding time: t2, and then the imprinted polysiloxane pattern on DLC film was processed with an electron cyclotron resonance (ECR) oxygen ion shower. However, we were not able to fabricate micro-gear patterns in high accuracy because of a remaining residual layer on the DLC film. Therefore we propose the removing process for the residual layer with trifluoromethane (CHF3) ion shower under the optimum conditions of 300 eV-ion energy and 4 min-etching time. As a result, we succeeded to fabricate concave DLC-based micro-gear patterns in high accuracy which has 30 µm-tip diameter and 1 µm-depth.

Robust micromachining of compliant mechanisms using silicides

We introduce an innovative sacrificial surface micromachining process that enhances the mechanical robustness of freestanding microstructures and compliant mechanisms. This process facilitates the fabrication, and improves the assembly yield of the out-of-plane micro sensors and actuators. Fabrication of a compliant mechanism using conventional sacrificial surface micromachining results in a non-planar structure with a step between the structure and its anchor. During mechanism actuation or assembly, stress accumulation at the structure step can easily exceed the yield strength of the material and lead to the structure failure. Our process overcomes this topographic issue by virtually eliminating the step between the structure and its anchor, and achieves planarization without using chemical mechanical polishing. The process is based on low temperature and post-CMOS compatible nickel silicide technology. We use a layer of amorphous silicon (a-Si) as a sacrificial layer, which is locally converted to nickel silicide to form the anchors. High etch selectivity between silicon and nickel silicide in the xenon difluoride gas (sacrificial layer etchant) enables us to use the silicide to anchor the structures to the substrate. The formed silicide has the same thickness as the sacrificial layer; therefore, the structure is virtually flat. The maximum measured step between the anchor and the sacrificial layer is about 10 nm on a 300 nm thick sacrificial layer.

Fabrication of High Aspect Ratio Silicon Nanochannel Arrays

We report a method of fabricating an array of high aspect ratio silicon nanochannels which is not dependent on nanolithography techniques and equipment. The method comprises etching of silicon micro-channels in an inductively coupled plasma system (ICP), followed by a thermal oxidation step where silicon is consumed during the process to further shrink the channel to nano dimensions. For the micro-channel formation, silicon dioxide is used as the etch mask during the ICP process where a high etch selectivity of 70:1 between silicon and silicon dioxide was achieved. By thermally oxidizing the etched silicon channels, a uniform array of nanochannels with lateral dimensions down to 40 nm was achieved with significantly high aspect ratio value of at least 65. The grown thermal oxide uniformly covers all surfaces of the silicon nanochannels.

Formation of silicon nanostructures with a combination of spacer technology and deep reactive ion etching

A new method of fabricating high aspect ratio nanostructures in silicon without the use of sub-micron lithographic technique is reported. The proposed method comprises two important steps including the use of CMOS spacer technique to form silicon nitride nanostructure masking followed by deep reactive ion etching (DRIE) of the silicon substrate to form the final silicon nanostructures. Silicon dioxide is used as the sacrificial layer to form the silicon nitride nanostructures. With DRIE a high etch selectivity of 50:1 between silicon and silicon nitride was achieved. The use of the spacer technique is particularly advantageous where self-aligned nanostructures with potentially unlimited lengths are formed without the need of submicron lithographic tools and resist materials. With this method, uniform arrays of 100 nm silicon nanostructures which are at least 4 μm tall with aspect ratio higher than 40 were successfully fabricated.

Investigation of Synchronized Pulsed Plasma for High Selective Etching of Silicon Nitride Spacers

not Available.

Dry etching characteristics of TaN absorber for extreme ultraviolet mask with Ru buffer layer

The extreme ultraviolet (EUV) mask using reflective optics has a structure totally different from that of the conventional mask. This study investigated the dry etching characteristics of the EUV mask layer in which TaN and Ru were used as the absorber and buffer layer, respectively. The TaN absorber etching requires high etch selectivity of TaN over Ru to achieve the high EUV reflectivity. In this work, the TaN etching rate was investigated with various halogen gases in the capacitively coupled plasma type etching system. The etching rates with the fluorinated gases were higher than that with the chlorinated gas. Ru could not be etched without oxygen in all of the considered etch gases. The etching rate of TaN and its etch selectivity to Ru were increased with the increase of RF power, pressure and SF6 gas flow ratio. When the real EUV mask specimens were 100% over etched under the highest selectivity etching condition, the Ru buffer layer still remained, which was confirmed by x-ray photoelectron spectroscopy analysis. The surface roughness of etched reflective mirror was very small, and the EUV reflectivity was equivalent to that of the reference mirror (EUV reflectivity is over 60%) which was confirmed by measuring the intensity and the diffracted pattern of 13.5 nm EUV obtained using x-ray charge coupled device camera. The Ru buffer layer could be removed by the O2 plasma used in the posterior photo resist ashing process without affecting the EUV reflectivity.

Highly Selective Etching of SnO<SUB>2</SUB> Absorber in Binary Mask Structure for Extreme Ultra-Violet Lithography

Among the core EUVL (extreme ultra-violet lithography) technologies for nanoscale patterning below the 30 nm node for Si chip manufacturing, new materials and fabrication processes for high-performance EUVL masks are of considerable importance due to the use of new reflective optics. In this work, the selective etching of SnO2 (tin oxide) as a new absorber material, with high EUV absorbance due to its large extinction coefficient, for the binary mask structure of SnO2 (absorber layer)/Ru (capping/etch stop layer)/Mo-Si multilayer (reflective layer)/Si (substrate), was investigated. Because infinitely high selectivity of the SnO2 layer to the Ru ESL is required due to the ultrathin nature of the Ru layer, various etch parameters were assessed in the inductively coupled Cl2/Ar plasmas in order to find the process window required for infinitely high etch selectivity of the SnO2 layer. The results showed that the gas flow ratio and V(dc) value play an important role in determining the process window for the infinitely high etch selectivity of SnO2 to Ru ESL. The high EUV-absorbance SnO2 layer, patternable by a dry process, allows a smaller absorber thickness, which can mitigate the geometric shadowing effects observed for high-performance binary EUVL masks.