High Etch Rate Research Articles

Angle-dependent ion-beam etching of RuAl thin films for structuring GHz-frequency electronics

The ruthenium aluminide (RuAl) alloy is a promising electrode material for wireless surface acoustic wave sensors working under harsh conditions at high temperatures. However, during the structuring of RuAl thin films using ion-beam etching, etched material can redeposit at the edges of the electrodes and form objects, so-called fences, on top of the structured features. These decrease the high-temperature stability and lead to an undesired alteration of the sensor performance. In this work, the angle-dependent ion-beam etching of RuAl thin films was investigated to inhibit the formation of such fence structures. The etch rate was determined as a function of the etching angle between ion-beam and sample surface in a range between 90° and 40°. Furthermore, finger structures with pitches below 500 nm, which are required for devices working in the intended GHz regime, were patterned to study the influence of the etching angle on the profile of the RuAl electrode fingers using transmission electron microscopy and energy-dispersive x-ray spectroscopy. The results show that an etching angle of 50° results in the highest etch rate. For etching angles of 50° and below, the width of the fences is reduced below 10 nm, so they break off during standard resist removal procedures. Such low etching angles lead to shadowed areas on the side of structured features in which unetched material remains. However, this material can be removed by using a two-step etching process combining a 50° step with a 90° step. This process is capable of structuring fence-free trapezoidal-shaped electrode finger profiles. Therefore, the developed process is well suited for the fabrication of high-temperature GHz-frequency RuAl electrodes.

Enhanced plasma etching using nonlinear parameter evolution

This study explores the development and characterization of plasma etching for sub-micron features using a nonlinear evolution of parameter in a three-step cyclic Bosch process. Comparing this nonlinear approach with traditional linear parameter evolution, we aimed to address issues such as bowing at the top of the features and narrowing at the bottom. Constant parameter etching produced tapered profiles, undercutting, and non-uniform scallops due to particle deflection. Linear parameter evolution partially mitigated these problems by balancing etch and deposition cycles and gradually increasing radio frequency power, achieving high selectivity to the photoresist. One nonlinear exponential evolution method resulted in a higher etch rate but caused slight damage to the top-side wall, while the etch depth was reduced. The other nonlinear method balanced the etch and deposition steps more effectively, achieving a comparable etch rate and selectivity to the linear method. Further optimization of this second method led to improved vertical profiles and controlled scallops, achieving greater depth, smoother sidewalls, and higher etch rates. This optimized technique successfully fabricated high aspect ratio periodic sub-micron structures with excellent uniformity across the wafer, demonstrating its potential for achieving even higher aspect ratios with thicker masks.

Enhancing Si1-XGex/Si Etch Rate Selectivity Using Etching Inhibitor in Radical Oxidation By Halide-Based Oxidant

As the technology node shrinks, innovation in the metal-oxide-semiconductor field-effect transistor (MOSFET) architecture has been required to mitigate the short-channel effects (SCE). Thus, planar FET had changed to FinFET and now gate-all-around FET (GAAFET) has been introduced with entering the 3-nm-generation. To fabricate GAAFET, selective etching of Si1-xGex- to Si-film is a key technology. According to the International Roadmap for Devices and Systems (IRDS™), the gate width of GAAFET is around 30 nm. Therefore, higher than 30 nm/min of etch rate for throughput and more than 400:1 of selectivity for acquiring a uniform Si-channel layer are required.As is well known, the etch rate in wet etching strongly depends on the standard reduction potential (SRP) of the oxidant. Our research group previously revealed the radical oxidation mechanism of sodium periodate (NaIO4) oxidant. In an acidic medium, NaIO4 can exist in periodate ion (IO4 -) form capable of generating hydroxyl radical (•OH). The high SRP value of hydroxyl radical (2.80 eV) compared to conventional oxidant, hydrogen peroxide (H2O2, 1.76 eV) and peracetic acid (PAA, 1.75 eV), resulted significantly high etch rate. In subsequent research, we introduced inhibitors reducing the Si-film etch rate to enhance Si1-xGex/Si etch rate selectivity when using sodium periodate as an oxidant.Acetic acid is commonly used as an additive in wet etchants to maintain uniform pH and control the etching of Si-film. However, it has several issues, strong vinegar odor, relatively large concentration to act, etc. Therefore, other additives are needed to substitute acetic acid. In selecting inhibitors, 2 factors are considered, i) scavenging effect for hydroxyl radical, and ii) hydrophobicity, as shown in Figure 1. Because the concentration of hydroxyl radical influences not only the Si1-xGex-film etch rate, but the Si-film etch rate, the scavenging effect of an inhibitor can reduce the film etch rate to enhance etch rate selectivity. Furthermore, the hydrophobicity part of inhibitors can build a hindrance layer on Si-film. Generally, Si-film has more hydrophobicity than Si1-xGex-film, inhibitors having hydrophobicity part are more prone to form a hindrance layer on Si-film than Si1-xGex-film. This results in the enhancement of Si1-xGex/Si etch rate selectivity by reducing Si-film considerably than Si1-xGex-film. The qualitative comparison of hydroxyl radical concentration depending on inhibitors and characterization methods to confirm the hindrance layer will be presented in detail. Acknowledgement This work was supported by the Technology Innovation Program (20022475, Development of wet Etchant capable of high selection etching in microprocesses below 10 nm) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) References [1] Lee, Seung-Jae, et al. "Extremely high selective Si1−xGex-film wet etchant generating highly dissolved oxygen via peracetic acid oxidant for lateral gate-all-around FETs with a logic node of less than 3-nm." Chemical Engineering Journal 475 (2023): 146257. Figure 1

Arc-enhanced glow discharge ion etching of WC-Co cemented carbide for improved PVD thin film adhesion and asymmetric cutting edge preparation of micro milling tools

Wear-resistant thin films on cutting tools require effective ion etching to enhance adhesion and thus extended tool service life. Arc enhanced glow discharge (AEGD) ion etching, characterized by high ionization degrees and high etch rates, was applied to ultrafine-grained WC-Co cemented carbide, commonly used for micromilling cutters. The effect of AEGD ion etching on the surface integrity of WC-Co and the resulting adhesion behavior of a TiAlSiN thin film was investigated by varying the etching time in comparison with conventional glow discharge (GD) ion etching. In addition, the impact of intensive etching on the cutting edge geometry of micro end cutters and, in turn, on the cutting performance in micromilling of hardened and annealed high-speed steel was evaluated.AEGD achieves remarkable etch rates of 12 nm/min at extended etching times, which are 100 times greater than conventional glow discharge (GD) ion etching. Prolonged AEGD ion etching for ≥30 min removes entire near-surface WC grains and exposes carbides beneath, resulting in increased surface roughness. After the etching process, polished WC-Co substrates exhibit a slight reduction in residual compressive stresses, which steadily decrease with increasing AEGD ion etching time. Furthermore, a TiAlSiN thin film demonstrates high adhesion on AEGD-etched surfaces compared to GD ion etching. Even a brief 5 min AEGD ion etching ensures the highest adhesion class according to the Rockwell C indentation test. Moreover, the intensive material removal results in significant changes in cutting edge geometry of micro end cutters, yielding substantial cutting edge rounding and an asymmetrical shape with form-factors Κ ≥ 2. In cutting tests, the resulting cutting edge geometries effectively reduce the wear formation and the associated wear-related increase in process forces during micromilling hardened and tempered powder metallurgical high-speed steel. In summary, AEGD ion etching emerges as a highly effective method for both enhancing thin film adhesion and preparing adapted asymmetrical cutting edge geometries for micromilling tools.

Investigation of silicon nitride for spacer via plasma-enhanced atomic layer deposition using a (tert-butylamino)dimethylsilane precursor

Silicon nitride (SiNx) has attracted considerable attention as a spacer in advanced semiconductor devices, owing to its superior barrier performance. However, the fabrication of SiNx films remains challenging, because of the corrosive byproducts generated when using chlorine precursors and impurities associated with the redeposition species of precursor ligands. The selection of precursor and optimization of the process parameters influence the film growth and improve the film properties. In this study, the (tert-butylamino)dimethylsilane (TBADMS) precursor and N2 plasma were introduced for the first time by plasma-enhanced atomic layer deposition (PEALD) to deposit SiNx films. We attempted to improve the film properties by adjusting the substrate temperature and investigated different growth mechanisms. The film deposited at 300 °C exhibited the most superior film properties, with an N/Si ratio close to ideal Si3N4, high film density, smooth surface, and low wet etch rate. The proposed growth mechanism demonstrates the influence of the initial surfaces and residual redeposition species removal within the film. Additionally, dielectric characterization indicates that films deposited at a higher temperature exhibit enhanced dielectric constant and reduced hysteresis (k = 7.2, ΔV = 0.6 V) in comparison to those (k = 4.9, ΔV = 1.2 V) deposited at lower temperature.

Size-Effect-Based Dimension Compensations in Wet Etching for Micromachined Quartz Crystal Microstructures.

Microfabrication technology with quartz crystals is gaining importance as the miniaturization of quartz MEMS devices is essential to ensure the development of portable and wearable electronics. However, until now, there have been no reports of dimension compensation for quartz device fabrication. Therefore, this paper studied the wet etching process of Z-cut quartz crystal substrates for making deep trench patterns using Au/Cr metal hard masks and proposed the first quartz fabrication dimension compensation strategy. The size effect of various sizes of hard mask patterns on the undercut developed in wet etching was experimentally investigated. Quartz wafers masked with initial vias ranging from 3 μm to 80 μm in width were etched in a buffered oxide etch solution (BOE, HF:NH4F = 3:2) at 80 °C for prolonged etching (>95 min). It was found that a larger hard mask width resulted in a smaller undercut, and a 30 μm difference in hard mask width would result in a 17.2% increase in undercut. In particular, the undercuts were mainly formed in the first 5 min of etching with a relatively high etching rate of 0.7 μm/min (max). Then, the etching rate decreased rapidly to 27%. Furthermore, based on the etching width compensation and etching position compensation, new solutions were proposed for quartz crystal device fabrication. And these two kinds of compensation solutions were used in the fabrication of an ultra-small quartz crystal tuning fork with a resonant frequency of 32.768 kHz. With these approaches, the actual etched size of critical parts of the device only deviated from the designed size by 0.7%. And the pattern position symmetry of the secondary lithography etching process was improved by 96.3% compared to the uncompensated one. It demonstrated significant potential for improving the fabrication accuracy of quartz crystal devices.

Cryogenic etching of positively tapered silicon pillars with controllable profiles

Fabrication of high aspect ratio silicon nanopillars is challenging for various applications. A cryogenic silicon etching process using SF6 and O2 plasma is investigated to create silicon nanopillars with 10 μm height and tens of nanometers apex. In the process, fluorine radicals react with silicon atoms, releasing volatile SiFx byproducts and then oxygen atoms interact with SiFx and deposit a SiOxFy film acting as an inhibitor. By adjusting the O2 concentration and the forward radio frequency power, this process modifies the formation of the SiOxFy passivation film and adjusts the bombardment of ions onto the inhibitor, resulting in the desired positive taper angles of silicon pillars. Two etching steps, with higher and lower O2 concentrations, are consecutively combined to create a sharp apex and a wide base. The results demonstrate the high etching rate and controllability of cryogenic etching to obtain high aspect ratio silicon pillars with desired profiles.

High-rate etching of silicon oxide and nitride using narrow-gap high-pressure (3.3 kPa) hydrogen plasma

We investigated the etching behavior of silicon oxide (SiO x ) and silicon nitride (SiN x ) in narrow-gap, high-pressure (3.3 kPa) hydrogen (H2) plasma under various etching conditions. Maximum etching rates of 940 and 240 nm min−1 for SiO x and SiN x , respectively, were obtained by optimizing the H2 gas flow rate. The dependence of the etching rate on gas flow rate implied that effective elimination of etching products is important for achieving high etching rates because it prevents redeposition. The sample surfaces, especially the oxide surfaces, were roughened and contained numerous asperities after etching. Etching rates of both SiO x and SiN x decreased as the temperature was raised. This suggests that atomic H adsorption, rather than H-ion bombardment, is an important step in the etching process. X-ray photoelectron spectroscopy revealed that the etched nitride surface was enriched in silicon (Si), suggesting that the rate-limiting process in high-pressure H2 plasma etching is Si etching rather than nitrogen abstraction. The etching rate of SiO x was three times higher than that of SiN x despite the higher stability of Si–O bonds than Si–N ones. One reason for the etching difference may be the difference between the bond densities of SiO x and SiN x . This study presents a relatively non-toxic, low-cost, and eco-friendly dry etching process for Si-based dielectrics using only H2 gas in comparison with the conventional F-based plasma etching methods.

Etching mechanism of amorphous hydrogenated silicon nitride by hydrogen fluoride

We report the etching mechanism of amorphous hydrogenated silicon nitride by hydrogen fluoride (HF) gas using density functional theory (DFT) calculations. Since silicon nitride films are deposited as amorphous with a significant amount of hydrogen, we constructed an amorphous substrate model with a hydrogen concentration of 25 at.% using molecular dynamics simulation and DFT calculations. We then created slab models with different degrees of fluorination and simulated all possible fluorination pathways. The pathways involving cleavage of Si–N or Si–Si bonds showed low activation energies of 0.90 eV or lower, while the pathways involving cleavage of a Si–H bond showed high activation energies of 1.54 eV or higher. NH3, SiF4, SiH2F2, and SiHF3 were released with low activation energies, indicating that etching would be favorable. Next, we modeled the formation and desorption of the (NH4)2SiF6 salt on the fluorinated surface. The salt formation was exothermic with low activation energies, consistent with self-limited etching at low temperatures. At temperatures of 152 °C or higher, (NH4)2SiF6 would desorb, leaving no solid residue, consistent with the high etch rate at elevated temperatures. Our DFT calculations using the amorphous hydrogenated slab model successfully explained the silicon nitride etching process, which could not be explained by a crystalline Si3N4 slab model.

Necking Reduction at Low Temperature in Aspect Ratio Etching of SiO2 at CF4/H2/Ar Plasma.

This study investigated the effect of temperature on the aspect-ratio etching of SiO2 in CF4/H2/Ar plasma using patterned samples of a 200 nm trench in a low-temperature reactive-ion etching system. Lower temperatures resulted in higher etch rates and aspect ratios for SiO2. However, the plasma property was constant with the chuck temperature, indicated by the line intensity ratio from optical emission spectroscopy monitoring of the plasma. The variables obtained from the characterization of the etched profile for the 200 nm trench after etching were analyzed as a function of temperature. A reduction in the necking ratio affected the etch rate and aspect ratio of SiO2. The etching mechanism of the aspect ratio etching of SiO2 was discussed based on the results of the surface composition at necking via energy-dispersive X-ray spectroscopy with temperature. The results suggested that the neutral species reaching the etch front of SiO2 had a low sticking coefficient. The bowing ratio decreased with lowering temperature, indicating the presence of directional ions during etching. Therefore, a lower temperature for the aspect ratio etching of SiO2 could achieve a faster etch rate and a higher aspect ratio of SiO2 via the reduction of necking than higher temperatures.

Etching of a fluoropolymer coating synthesized by the hot wire chemical vapor deposition method in a low-frequency induction discharge plasma

The process of plasma etching for the formation of a biphilic pattern in a continuous homogeneous fluoropolymer coating on a copper substrate is studied. Argon or oxygen plasma of low frequency ferromagnetic amplified induction discharge is used to etch a fluoropolymer coating. Plasma etching was carried out through a mask with parallel slits. The etching rate in argon plasma was 10 nm/min, the etching rate in oxygen plasma was 60 nm/min. Biphilic surfaces were obtained, consisting of fluoropolymer strips on a copper surface. It has been shown that when using both argon plasma and oxygen plasma, it is possible to create biphilic surfaces by etching a continuous homogeneous fluoropolymer coating through a mask. Moreover, oxygen plasma is better suited for this because it has a higher etching rate and weakly changes the wettability of the surface.

Novel Wet Etchant for Highly Selective Etching of Si1-XGex-Film to Si-Film with Sodium Periodate Oxidant

As the technology node of complementary-metal-oxide-semiconductor (CMOS) transistor has been scaled down to 3 nm, CMOS transistor’s structure has been changed from fin field-effect transistors to gate-all-around field-effect transistors (GAAFETs) to improve the short-channel effects by enhancing gate controllability. In addition, dynamic random-access memory (DRAM) also has been faced the limitation in scaling-down of a capacitor having high aspect ratio and in migrating from 6 to 4F2 cell increasing floating body effects. To overcome the limitation, 3-dimensional (D) DRAM structure having GAA structure has been researched as an alternative structure to the conventional 6F2 cell structure. In fabricating GAAFETs and 3-D DRAM, two major fabrication processes are needed, i) epitaxial growth of Si1-xGex/Si multi-stacks, and ii) selective etching of Si1-xGex films to Si films. For process i), low Ge concentration (<30%) is desirable for reducing stacking faults and defects at the interfaces between Si1-xGex and Si. In addition, for process ii), considerably high etch rate (>30nm/min) and etch selectivity of Si1-xGex films to Si films (>300:1) are required. In particular, for etching Si1-xGex grown on Si layer of a sacrificial layer, a high selectivity, high etch rate and isotropy of wet chemical etching are strongly required. In general, among the components of wet chemical etchant consisting of oxidant, etching accelerator (i.e., HF), selectivity enhancing agent (i.e., acetic acid), and deionized water, the higher standard reduction potential (SRP) of oxidant leads the higher selectivity and higher etch rate of Si1-xGex films to Si films due to the increase in the potential differences of SRP and Si1-xGex valence band edge. For the case of a conventional wet etchant using peracetic acid (PAA) or hydrogen peroxide (H2O2) as an oxidant, their SRP are ~1.75 and ~0.69 eV, respectively. However, its selectivity and etch rate of Si1-xGex films to Si films are insufficient at low Ge concentration of Si1-xGex despite the high SRP value of PAA and H2O2 because the bandgap energy of Si1-xGex increase with decreasing Ge concentration.In our research, therefore, we suggested a novel oxidant, sodium periodate (NaIO4) to enhance the etch rate and the selectivity of wet etchant based on the concept of radical generation. We investigated the dependencies of Si-, Si0.7Ge0.3-film etch rate and selectivity on oxidant species, and dependencies of lateral etch rate of Si0.7Ge0.3/Si multi-stack structures on oxidant species. This was motivated by that NaIO4 generates radicals in acidic medium, such as iodyl (IO3 •) and reactive oxygen species (i.e., the superoxide radical (O2 •–) and hydroxyl (•OH) radical), as shown in Fig. 1. SRP of NaIO4 itself has relatively low (~1.60 eV) compared to PAA (~1.75 eV), IO3 •, O2 •– and •OH radicals generated from NaIO4 have higher SRP (O2 •–: ~2.80 eV and •OH: ~2.42 eV), which resulted in a higher etch rate at lower Ge concentration less than 30%.For the experiments, the Si0.7Ge0.3 layer grown on Si and 3-layer Si0.7Ge0.3/Si multi-stack wafers were grown by using ultra-high-vacuum chemical vapor deposition (EUREKA, JUSUNG ENGINEERING). Coupon wafers with 1.5 × 1.5 cm2 of Si0.7Ge0.3 and Si substrate (reference group), and patterned wafers of 3-layer Si0.7Ge0.3/Si multi-stack layers with a line width of 10 μm were prepared and then all samples were dipped in the etchant solutions for 1 min at room temperature. The thickness of the samples was characterized by using spectroscopic ellipsometry (V-VASE, J.A. Woollam). In addition, after etching of the 3-layer Si0.7Ge0.3/Si multi-stack structures, a lateral etch rate were characterized by using field-emissive scanning electron microscope (Helios 5 CX, Thermofisher).It was confirmed that our novel etchant using NaIO4 as an oxidant demonstrated extremely high etch rate for Si0.7Ge0.3 film (140 nm/min), whereas conventional etchant using oxidant PAA and H2O2 demonstrated the etch rate of 5.7 and 2.4 nm/min respectively. In addition, the selectivity between the Si0.7Ge0.3- and Si films etched by using the NaIO4 oxidant was much higher (318:1) than that etched by PAA and H2O2 oxidant (29:1 and 6:1), as shown in Fig. 2, which sufficiently satisfied the requirement of etch rate (>30nm/min) and selectivity (300:1) for fabricating GAAFETs. The lateral etch rate of 3-layer Si0.7Ge0.3/Si multi-stack, mechanism on radical generation of NaIO4, and the characterization method to quantify radicals will be presented in detail. Acknowledgement This work was supported by the Technology Innovation Program (20022467, Development of Wet Etchant and Core Materials for Next Generation Semiconductor Manufacturing Process below 10 nm) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) Figure 1

(Invited) The Use of Plasmas for Isotropic Atomic Layer Etching

Atomic layer etching (ALE) is set to be a vital part of the advanced semiconductor manufacturing toolbox, known for its precise control of the film thickness and minimal damage. These benefits are possible due to the sequential self-limiting half-cycles that are employed within an ALE process. Initially, ALE was underestimated due to low etch rates, but it is now experiencing a renaissance due to the requirements imposed by further downscaling.1 The ALE community is mostly divided into two groups: plasma anisotropic and thermal isotropic etching. 2 In this work, the focus is on exploring isotropic plasma ALE, which is a relatively unexplored direction. This approach involves using plasma radicals to modify and/or etch material isotropically, while minimizing the directional ion component of the plasma. Isotropic plasma ALE can offer several benefits over strictly thermal ALE, such as higher etch rates, lower operating temperatures, and the ability to etch more resistant materials.In this talk we will first address some of the different techniques employed for plasma isotropic ALE in the literature. Subsequently, we will discuss our own work, which has focused on two isotropic plasma ALE chemistries. The first involves alternating between plasma fluorination and ligand-exchange half-cycles, this ALE chemistry has been found to be effective for etching Al2O3, HfO2, AlN, and GaN films.3,4 Surface contaminants and roughness were found to be reduced post ALE, an aspect that is particularly important for AlN and GaN films that are used in quantum, power semiconductor and LED applications. The second approach involves using diketone (e.g. acetylacetone, hexafluoroacetylacetone) doses followed by either H2 or O2 plasma exposures for ALE of Al2O3 and ZnO.5 The diketone in this process acts to etch the surface, however due to competitive adsorption of different diketone orientations an etch inhibition layer forms. The plasma step is then utilized to clean the surface, removing the self-limiting inhibitor layer, enabling etching to continue in the next cycle. This ALE chemistry diverges from the typical modification/removal ALE cycle, where a modified layer if often observed on the material post ALE. In comparison the diketone ALE chemistry does not rely on modification of the surface making it an ideal process for surface cleaning. This approach provides improved selectivity over the plasma fluorination process and also enables smoothing.Plasma isotropic ALE is a growing part of the ALE community that can help accelerate the adoption of ALE in academia and industry. The potential benefits of ALE are only just beginning to be explored, and more processes are needed to etch the ever-increasing range of materials utilized in IC manufacturing. Kanarik, K. J., Tan, S. & Gottscho, R. A. Atomic Layer Etching: Rethinking the Art of Etch. J Phys Chem Lett 9, 4814–4821 (2018).George, S. M. Mechanisms of Thermal Atomic Layer Etching. Acc Chem Res 53, 1151–1160 (2020).Chittock, N. J. et al. Isotropic plasma atomic layer etching of Al2O3 using a fluorine containing plasma and Al(CH3)3. Appl Phys Lett 117, 162107 (2020).Wang, H., Hossain, A., Catherall, D. & Minnich, A. J. Isotropic plasma-thermal atomic layer etching of aluminum nitride using SF6 plasma and Al(CH3)3. 1–14 (2022) doi:arXiv.2209.00150.Mameli, A., Verheijen, M. A., Mackus, A. J. M., Kessels, W. M. M. & Roozeboom, F. Isotropic Atomic Layer Etching of ZnO Using Acetylacetone and O2 Plasma. ACS Appl Mater Interfaces 10, 38588–38595 (2018).

Morphological and Electrical Characterization of AlGaN/GaN Heterostructures Modified By Atomic Layer Etching

Modern microelectronic components for high-power and high-frequency applications based on III-V compound semiconductors offer high break down voltage (GaN: 5 MV/cm and AlN: 15 MV/cm) at low specific on-resistance. However, it requires reliability and reproducibility of the production processes. Going to higher frequencies (5 GHz and beyond) and more integration in consumer electronics, smaller structure sizes are needed. This is going along with increasing demands on the manufacturing processes like dry etching. The main goal is to reach smaller and high controllable etching rates, going down to single atomic layers, low damage, and minimized surface roughness. Atomic layer etching (ALE) represents a key technology in order to achieve such requirements.An ALE process consists of two independent steps forming a repeatable cycle with a specific etching amount per cycle (EPC). First a surface modification is done by a chemical precursor i.e., adsorbing or oxidizing the surface. The second step is the removal of the modified layer, either physically by low energy non-reactive ion bombardment (Plasma Enhanced ALE [PEALE]) or chemically by a reactive species (Thermal ALE). The two steps are separated by an inert gas purge. This purging grants the removal of the chemistry after the first step, preventing further chemical reaction and transporting the chemical products out of the chamber after the second step.In this study, a PEALE conducted on different tools is used, for gate and contact recess study in a AlGaN/GaN heterostructure to form high electron mobility transistors (HEMT) with reduced ohmic contact resistance and threshold voltages. The results show a reduction of ohmic contact resistance at reduced forming temperatures and a linear dependence of the threshold voltage on gate recess depth. In order to determine the etching rate and roughness, atomic force microscopy (AFM) measurements were performed.The PEALE module is either integrated into a cluster tool consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD) or done in a combined ALD/ALE chamber. This opens the possibility of etching and depositing in-situ, reducing contamination and degradation of the substrate material.By this means, metal insulator semiconductor (MIS)-HEMTS with a recessed gate are studied. The monitoring of the individual processes is achieved by test structures like transfer length method structures (TLM) and metal oxide semiconductor (MOS), which showed the improved electric performance of these devices and may indicate unwanted interface issues, respectively. Additional, pre- and post-treatments could improve the interfaces further. The results will be presented and discussed in terms of ALE process development and optimization.This work was financially supported within the ALEStar project by the government of the Free-state of Saxony and the European Regional Development Fund under grant no. SAB 100402929.

(Invited) Novel Surface Reactions in Low-Temperature Regime for High-Aspect-Ratio Dielectric Etching

The most critical issue to achieve High-Aspect-Ratio (HAR) dielectric etching is the transport of both radicals and ions to the bottom of a feature [1]. Current HAR dielectric etching uses fluorocarbon and hydrofluorocarbon gases combined with high applied bias power. However, the etch rate drastically decreases at high depth due to the decline of radicals being supplied to the etch front. Alternative methods have long been required to solve this problem. To address the radical transport issue, we propose adopting a novel precursor with low molecular weight to enhance Knudsen transport. In addition, cryogenic temperature regimes are also known to enhance etch rates [2][3] but have not yet been implemented for HAR dielectric etching. In this work we evaluated a novel precursor in cryogenic temperature regime for HAR dielectric etching. For the first time, we demonstrate a synergy effect between cryogenic temperature and this novel precursor by successfully developing an innovative HAR dielectric etch process. We confirmed that this process is capable of etching beyond a ten-micron depth for a 3D-NAND channel hole with a hundred nanometer critical dimension in diameter, thus an aspect ratio of over one hundred to one. The key to enabling high etch rate is strongly correlated with the adsorption of the precursor on the surface, which is enhanced at cryogenic temperature. Detailed surface adsorption reaction mechanisms will be described in the conference. This new process not only enables higher etch rate, higher selectivity and higher aspect ratio etching capability, but also significantly shortens the process time with 84% carbon footprint reduction of greenhouse gas emissions.[1] K. Ishikawa, et al., Jpn. J. Appl. Phys. Vol. 57, No. 6S2, 06JA01, (2018).[2] T. Ohiwa, et al., Jpn. J. Appl. Phys. Vol.31, p.405, (1992).[3] R Dussart, et al., J. Phys. D: 47, 123001, (2014).

Advanced Etching Techniques of LiNbO3 Nanodevices.

Single LiNbO3 (LNO) crystals are widely utilized in surface acoustic wave devices, optoelectronic devices, and novel ferroelectric memory devices due to their remarkable electro-optic and piezoelectric properties, and high saturation and remnant polarizations. However, challenges remain regarding their nanofabrication that hinder their applications. The prevailing etching techniques for LNO encompass dry etching, wet etching, and focused-ion-beam etching, each having distinct merits and demerits. Achieving higher etching rates and improved sidewall angles presents a challenge in LNO nanofabrication. Building upon the current etching researches, this study explores various etching methods using instruments capable of generating diverse plasma densities, such as dry etching in reactive ion etching (RIE) and inductively coupled plasma (ICP), proton exchange-enhanced etching, and wet chemical etching following high-temperature reduction treatment, as well as hybrid dry and wet etching. Ultimately, after employing RIE dry etching combined with wet etching, following a high-temperature reduction treatment, an etching rate of 10 nm/min and pretty 90° sidewall angles were achieved. Furthermore, high etching rates of 79 nm/min with steep sidewall angles of 83° were obtained using ICP dry etching. Additionally, using SiO2 masks, a high etching rate of 108 nm/min and an etching selectivity ratio of 0.86:1 were achieved. Distinct etching conditions yielded diverse yet exceptional results, providing multiple processing paths of etching for the versatile application of LNO.

Influence of the Chemical Composition and Topography of the Ti6Al7Nb Surface Etched in Fluorine Plasma on Its Selected Properties

Herein, a new way of the surface modification of Ti6Al7Nb alloy in fluorine plasma is presented using the mask made of stainless steel and its influence on the selected properties, including chemical composition, topography, and tribological ones. Depending on the etching process parameters, different characteristics of the surfaces are obtained. The higher is the value of the negative bias, the less fluorine concentration on the etched surface and higher etching rates. Etching using the SF6 gas shows bigger etching rates in comparison to the etching using the CF4 gas. Chemical composition of the modified surfaces shows greater impact on tribological characteristics than topography parameters. The lowest wear rate is observed for the sample modified using the CF4 gas.

Fabrication of 4H-SiC piezoresistive pressure sensor for high temperature using an integrated femtosecond laser-assisted plasma etching method

The processing, particularly, etching of brittle, hard, and anti-corrosion materials represented by the third-generation wide bandgap semiconductor silicon carbide (SiC), is a significant challenge. Although SiC has excellent electrical, mechanical, and chemical properties, the difficulty of processing limits its application in various sensor devices. To solve this problem, in this study, an integrated processing method of femtosecond laser-assisted SiC dry etching is proposed, which realizes high surface quality and high rate etching of the SiC microstructure. Specifically, the effects of different laser processing parameters on the processing effect were first studied through orthogonal experiments. Experiments indicate that compared with laser power and laser scan times, laser processing speed has a more obvious impact on the processing effect. Subsequently, considering the elastic modulus anisotropy of SiC, a 5 MPa piezoresistive pressure sensor chip was designed. Using the proposed composite processing method, a chip sensitive diaphragm was obtained. The diaphragm thickness and diameter are 76 μm and 1700 μm respectively. The overall sensor chip dimension was 4000 μm × 4000 μm × 350 μm. Static tests demonstrated that the sensor have excellent performance with sensitivity of 6.8 mV/MPa, linearity of 0.69% FS, and repeatability of 0.078% FS. In addition, by designing high-temperature packaging, the sensor achieved a pressure test at 400 °C. This study verifies the feasibility of the composite processing method, realizes the fabrication and measurement of high-temperature pressure sensors, and provides a reference for the micro-and nanostructure processing of various SiC sensors.

Computational fluid dynamics modeling of a wafer etch temperature control system

Next-generation etching processes for semiconductor manufacturing exploit the potential of a variety of operating conditions, including cryogenic conditions at which high etch rates of silicon and very low etch rates of the photoresist are achieved. Thus, tight control of wafer temperature must be maintained. However, large and fast changes in the operating conditions make the wafer temperature control very challenging to be performed using typical etch cooling systems. The selection and evaluation of control tunings, material, and operating costs must be considered for next-generation etching processes under different operating strategies. These evaluations can be performed using digital twin environments (which we define in this paper to be a model that captures the major characteristics expected of a typical industrial process). Motivated by this, this project discusses the development of a computational fluid dynamics (CFD) model of a wafer temperature control (WTC) system that we will refer to as a “digital twin” due to its ability to capture major characteristics of typical wafer temperature control processes. The steps to develop the digital twin using the fluid simulation software ANSYS Fluent are described. Mesh and time independence tests are performed with a subsequent benchmark of the proposed ANSYS model with etch cooling system responses that meet expectations of a typical industrial cooling system. In addition, to quickly test different operating strategies, we propose a reduced-order model in Python based on ANSYS simulation data that is much faster to simulate than the ANSYS model itself. The reduced-order model captures the major features of the WTC system demonstrated in the CFD simulation results. Once the operating strategy is selected, this could be implemented in the digital twin using ANSYS to view flow and temperature profiles in depth.

Computational approach for plasma process optimization combined with deep learning model

As semiconductor device structures become more complex and sophisticated, the formation of finer and deeper patterns is required. To achieve a higher yield for mass production as the number of process steps increases and process variables become more diverse, process optimization requires extensive engineering effort to meet the target process requirements, such as uniformity. In this study, we propose an efficient process design framework that can efficiently search for optimal process conditions by combining deep learning (DL) with plasma simulations. To establish the DL model, a dataset was created using a two-dimensional (2D) hybrid plasma equipment model code for an argon inductively coupled plasma system under a given process window. The DL model was implemented and trained using the dataset to learn the functional relationship between the process conditions and their consequential plasma states, which was characterized by 2D field data. The performance of the DL model was confirmed by comparison of the output with the ground truth, validating its high consistency. Moreover, the DL results provide a reasonable interpretation of the fundamental features of plasmas and show a good correlation with the experimental observations in terms of the measured etch rate characteristics. Using the designed DL, an extensive exploration of process variables was conducted to find the optimal processing condition using the multi-objective particle swarm optimization algorithm for the given objective functions of high etch rate and its uniform distribution. The obtained optimal candidates were evaluated and compared to other process conditions experimentally, demonstrating a fairly enhanced etch rate and uniformity at the same time. The proposed computational framework substantially reduced trial-and-error repetitions in tailoring process conditions from a practical perspective. Moreover, it will serve as an effective tool to narrow the processing window, particularly in the early stages of development for advanced equipment and processes.