Higher Number Of Bits Research Articles

Multi-Threshold Inertial Switch for Quantitative Acceleration Measurements

This paper presents a multi-threshold inertial switch demonstrated experimentally and through simulation. A laterally-driven multi-threshold inertial switch based on SOIMUMPs has been fabricated. The device has been tested by a drop-table test system under different shock accelerations with various amplitudes and pulse widths. In addition to experimental data, finite element simulation has been used to further assess the device’s performance. The designed switch is a 2-axis device capable of triggering in all directions in a single plane. This work demonstrates that the designed inertial switch with 3 threshold levels can perform quantitative acceleration measurements while saving power when not activated. The multi-threshold inertial switch can sense a shock range of 800g–2600g. The same device principle can be extended for a higher number of bits. The axial disturbance performance shows that the inertial switch has high single-axial sensitivity and low axial cross-talk.

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

A compact half butterfly chipless RFID tag based on image theory with DER analysis

In this paper, a compact RFID chipless structure is designed, simulated, and fabricated. Image theory has been used to reduce the structure of the RFID tag so that it halves the tag and creates a PEC wall having the same resonant frequencies. In other words, each symmetric structure by this method is half the size with features similar to the original structure. The proposed structure has a ratio of area to lambda equal to 0.05 in which there are nine resonances in a frequency band of 4.3–8.5 GHz with dimensions of 14 × 7 mm2 in a bit density of 9.18 bit/cm2 and fabricated on Rog4003 substrate. The bit density for the full structure was equal to 4.59 bit/cm2. The original and proposed structures have similar resonances that indicate the accuracy of the proposed method. Also, this method can be used to create a label with a higher number of bits. The simulation results using HFSS software were in good agreement with the measurement results. Furthermore, the calculated detection error rate of the proposed structure was lower than the original one.

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of xor–xnor circuit. In this article, a high-speed, low-power 10-T xor–xnor circuit is proposed, which provides full swing outputs simultaneously with improved delay performance. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. The proposed circuit reduces the power delay product (PDP) at least by 7.5% than that of the available xor–xnor modules. Four different designs of FAs are also proposed in this article utilizing the proposed xor–xnor circuit and available sum and carry modules. The proposed FAs provide 2%–28.13% improvement in terms of PDP than that of other architectures. To measure the driving capabilities, the proposed FAs are embedded in 2-, 4-, and 8-bit cascaded full adder (CFA) structures. Results show that two of the proposed FAs provide the best performance for a higher number of bits among all the FAs.

An Algorithm for Automatic Recogniton of Digital QAM Modulations

Abstract This paper proposes a new Matlab-developed algorithm for automatic recognition of digital modulations using the constellation of states. Using this technique the automatic distinction between four digital modulation schemes (8-QAM, 16-QAM, 32-QAM and 64-QAM) was made. It has been seen that the efficiency of the algorithm is influenced by the type of modulation, the value of the signal-to-noise ratio and the number of samples. In the case of an AWGN noise channel the simulation results indicated that the value of SNR (signal-to-noise ratio) has a small influence on the recognition rate for lower-order QAM (8-QAM and 16-QAM). The length of the signal may change essentially the recognition rate of this algorithm especially for modulations with a high number of bits per symbol. Consequently, for the 64-QAM modulation in a case of 25dB signal-to-noise ratio the recognition rate is doubled if the sample rate is incresed from 5400 to 80640.

IMAGE HIDING ON HIGH FREQUENCY SPEECH COMPONENTS USING WAVELET PACKET TRANSFORM

This paper propose a method for security threw hiding the image inside the speech signal by replacing the high frequencycomponents of the speech signal with the data of the image where the high frequency speech components are separated and analyzed usingthe Wavelet Packet Transform (WPT) where the new signal will be remixed to create a new speech signal with an embedded image. The algorithm is implemented on MATLAB 15 and is designed to achieve best image hiding where the reconstruction rate was more than 94% while trying to maintain the same size of the speech signal to overcome the need for a powerful channel to handle the task. Best results were achieved with higher speech resolution (higher number of bits per sample) and longer periods (higher number of samples in the media file).

LINEAR MICROSTRIP RESONATOR FOR UWB RFID TAG

The data storage capacity is directly proportional to the number of bits on board of the tag. The main challenge in UWB tag development is to maintain higher number of bits while keeping the tag within the standard size. Higher number of bits also ensures more security and anti-tempering protection of the tagging. In addition, reducing the dimensions of the tag can lead to the possibilities of fully replacing the existing barcode identification system. A new type of planar shorted parallel coupled line microstrip resonator which can replace the existing planar rectangular type resonator has been proposed in this paper. The theoretical approximation and simulation have been performed. A 20-bit resonator has been designed and developed that works between 4.6GHz and 8.1GHz. It is found that the bit density per unit area (cm2) is about 6.67 bit/cm2 has been achieved. The simulation has been performed by CST MWS 2017. The results would motivate the researchers to develop a higher bit density UWB passive RFID tag.

Competitive Brain Emotional Learning

Brain emotional learning (BEL) methods are a recently developed class of emotional brain-inspired algorithms, that enjoy feed-forward computational complexity on the order of O(n). BEL methods suffer from a major drawback related to the non-linear problem solving ability, i.e. they cannot solve n-bit parity problems in which $$\hbox {n} \ge 3$$nź3. The present paper proposes a competitive BEL (C-BEL) capable of accommodating a higher number of bits in the parity problem. The proposed C-BEL is inspired by the competitive property of neucortex's neurocircuits. The method is tested on n-bit parity, function approximation and a pattern recognition problem. Various comparisons with the reinforcement BEL (R-BEL), supervised BEL (S-BEL), evolutionary BEL (E-BEL), a Boltzmann machine and a convolutional neural network indicate the superiority of the approach in terms of its higher ability in non-linear problem solving, function approximation and pattern recognition.

Encoder Improvement for Simple Amplitude Fully Parallel Classifiers Based on Grey Codes

The present article describes functionality of real-time classifier usable for data flow statistical parameters calculations, different modulation types symbol detecting and in other applications, where the fastest association of input signals sample is required with one of the predefined categories. The effective implementation of encoder with high number of bits for fully parallel classifier is provided based on Gray codes (Gray, 1953). The work is concluded with comparative analysis of encoder standard implementation and its optimized version for FPGAs manufactured by Xilinx and Altera companies.

Ultra-Low Power Digitally Operated Tunable MEMS Accelerometer

This paper presents the concept as well as fabrication and measurement results for a new class of MEMS accelerometers that can be operated directly by a digital processor without the need for an analog front end. Elimination of the analog front end for such digitally operated accelerometers can significantly lower the sensor power consumption. The accelerometer consists of a proof mass and a number of parallel plate electrostatic actuators that can be turned ON and OFF in a sequential manner by a digital controller. Consequently, an ON or OFF output is provided for each input condition based on an output electrode making contact with the biased proof mass. Following a simple switching algorithm, a binary search can be performed by the digital controller to find the acceleration as a binary number. Furthermore, this paper also estimates the operating power consumption for such an accelerometer. A simple 2-b version of such accelerometers has been successfully fabricated and operated in the 0-1-g range. The same device concept and the configuration can be enhanced to higher number of bits.

Rank Determination by Winner-Take-All Circuit for Rank Modulation Memory

Multilevel-cell (MLC) memory technologies have achieved a great improvement in increasing demand for a high-density memory. As the memory cells utilize a higher number of bits per cell, they have been faced with some problems, such as accurate charge placement and measurement, which slow down programming processes. To overcome these problems, the new data representation technology, rank modulation coding, is employed for MLC memories. For rank modulation memory, a fast and accurate rank reading among multiple cells is one of the most important functions to be achieved to serve an efficient nonvolatile memory. The existing rank determination methods that compare two currents (memory current and ramp down current) and an array of winner-take-all (WTA) rank determination showed their own limitation in terms of mismatch impacts and area consumption. If the rank determination speed can be improved and the circuits are not affected by the possible impact of mismatch, the rank modulation memory will be a more practical memory as a next-generation memory. This brief presents a new rank read circuitry with much faster rank read time. The read time for 16 cells' ranks is 600 ns, which is much faster than the existing ways. This rank determinator adopted an advanced WTA circuit for the rank read circuitry.

Optical logic gates based on semiconductor optical amplifier Mach–Zehnder interferometer: design and simulation

All-optical logic gates are designed to extend the existing design to a higher number of bits, to use the same gate in multifunctions, and to add new gate designs. This type of gate is based on semiconductor optical amplifier (SOA) nonlinearities, since the SOA can provide a strong change of the refractive index together with high gain. The SOA is used with a Mach–Zehnder interferometer (MZI) forming an SOA-MZI structure which is used to perform the logic gates XOR, NOR, OR, and XNOR. Two binary input data signals are used with different number of bits (4, 6, 8, and 16 bit) at 10 Gbps. This work includes the study of the effect of the number of bits on the received power, minimum bit error rate, and maximum Q-factor.

FPGA-BASED INTERFACING FOR 8-BIT AND 32-BIT ELECTRONIC DEVICES

Most of the earlier electronic devices used buses with lesser number of bits but with the advancement in technology, devices having buses with larger number of bits are available in the market. Thus, there is an urging need to interface both these old and new technologies. In this paper, an interfacing unit has been proposed to interface the devices using buses with lower number of bits and higher number of bits. In the present work, two types of circuits are used for interfacing these devices; those have been termed as UPSIZER and DOWNSIZER circuit. Upsizer concatenates the bits generated by a lower bit device and sends it to a higher bit device. On the other hand, Downsizer divides the bits generated by higher bit devices and send it to lower bit devices.

Ingestive Behavior of Cows in Pastures Andropogon gayanus and Brachiaria decumbens in Southern State of Piauí, Brazil

The research was conducted at the experimental farm of the Agricultural College of Bom Jesus, which is located at 135 km 3 BR, in the region of the valley Gurguéia southern state of Piauí. We used 10 crossbred cows of Holstein x Gir. The experimental design was completely randomized with two treatments (the pastures of grasses Andropogon gayanus and Brachiaria decumbens), with five replicates (five animals per treatment). The trial lasted five days. Two evaluations were made with duration of 24 hours each, conducted during a day, and the average of the two ratings was used in the statistical analyzes. The evaluations were performed on 20 to 24 July 2013. The cows grazed more time in the morning around 7-10 hours and late afternoon extending into the night with peak until 19:00 hours. The idle time was greater at the end of the night that matches the period of reduced grazing activity. The cows grazed more time during the day in the pasture of Brachiaria decumbens (8.53 hours) compared to pasture Andropogon gayanus (8.03 hours). With respect to time grazing night, the situation was reversed, the animals grazed longer during the day and slowed down during the night (3.16 hours grazing) in the pasture of Brachiaria decumbens. The animals had a higher number of bits (14128.92) in grazing Brachiaria decumbens compared to Andropogon gayanus (10134.00).

Large-scale high-resolution computational validation of novel complexity models in linear cryptanalysis

Linear cryptanalysis is one of the few major attack techniques in today’s cryptography. Every new cipher comes with strong arguments against it. Still, some recent relevant ciphers such as the ISO/IEC lightweight block cipher present proved to be particularly vulnerable to linear cryptanalysis. Since most attacks published today — including the linear cryptanalysis — have complexities beyond practical reach, the evaluation of their complexities has to rely on rather theoretical computational models. The latter are often based on unproven and not always precise assumptions that might result in inexact models.Very recently, in FSE’13, it has been demonstrated that the standard models the cryptanalysts have been relying on for a long time in linear attacks, while being quite adequate for a wide range of parameters, tend to fail when the attack to be evaluated tries to recover a high number of bits in the secret key of the cipher. However, this is actually the top-priority goal of any adversary. To amend the standard models that proved somewhat inaccurate in this crucial parameter range, a new model has been proposed based on an enhanced wrong key randomization hypothesis. However, this model has been verified only for quite small ciphers of 20-bit block size. At the same time, in the real-world applications, the block size of a cipher is usually 32 bits and higher. Thus, the experimental verification of the model remains quite limited.In this article, we aim to bridge this gap and study this novel model for much bigger ciphers. We are able to perform its computational validation for cipher with up to 36 bits with meaningful resolution. Our work confirms that the new model of FSE’13 is significantly more accurate for a wide range of cipher parameters.

General Structure Design for Fast Image Processing Algorithms Based upon FPGA DSP Slice

Abstract Increasing the speed and accuracy for a fast image processing algorithms during computing the image intensity for low level 3x3 algorithms with different kernel but having the same parallel calculation method is our target to achieve in this paper. FPGA is one of the fastest embedded systems that can be used for implementing the fast image processing image algorithms by using DSP slice module inside the FPGA we aimed to get the advantage of the DSP slice as a faster, accurate, higher number of bits in calculations and different calculated equation maneuver capabilities. Using a higher number of bits during algorithm calculations will lead to a higher accuracy compared with using the same image algorithm calculations with less number of bits, also reducing FPGA resources as minimum as we can and according to algorithm calculations needs is a very important goal to achieve. So in the recommended design we used as minimum DSP slice as we can and as a benefit of using DSP slice is higher calculations accuracy as the DSP capabilities of having 48 bit accuracy in addition and 18 x 18 bit accuracy in multiplication. For proofing the design, Gaussian filter and Sobelx edge detector image processing algorithms have been chosen to be implemented. Also we made a comparison with another design for proofing the improvements of the accuracy and speed of calculations, the other design as will be mentioned later on this paper is using maximum 12 bit accuracy in adding or multiplying calculations.

A Framework for the Assessment of Temporal Artifacts in Medium Frame-Rate Binary Video Halftones

Display of a video having a higher number of bits per pixel than that available on the display device requires quantization prior to display. Video halftoning performs this quantization so as to reduce visibility of certain artifacts. In many cases, visibility of one set of artifacts is decreased at the expense of increasing the visibility of another set. In this paper, we focus on two key temporal artifacts, flicker and dirty-window-effect, in binary video halftones. We quantify the visibility of these two artifacts when the video halftone is displayed at medium frame rates (15 to 30 frames per second). We propose new video halftoning methods to reduce visibility of these artifacts. The proposed contributions are (1) an enhanced measure of perceived flicker, (2) a new measure of perceived dirty-window-effect, (3) a new video halftoning method to reduce flicker, and (4) a new video halftoning method to reduce dirty-window-effect.

On performance of lossless compression for HDR image quantized in color space

High dynamic range (HDR) image requires a higher number of bits per color channel than traditional images. This brings about problems to storage and transmission. Color space quantization has been extensively studied to achieve bit encodings for each pixel and still yields prohibitively large files. This paper explores the possibility of further compressing HDR images quantized in color space. The compression schemes presented in this paper extends existing lossless image compression standards to encode HDR images. They separate HDR images in their bit encoding formats into images in grayscale or RGB domain, which can be directly compressed by existing lossless compression standards such as JPEG, JPEG 2000 and JPEG-LS. The efficacy of the compression schemes is illustrated by presenting extensive results of encoding a series of synthetic and natural HDR images. Significant bit savings of up to 53% are observed when comparing with original HDR formats and HD Photo compressed version. This is beneficial to the storage and transmission of HDR images.

Methodology for the design of a 4-bit soft-hardware-logic circuit based on neuron MOS transistors

As soft-hardware-logic circuits had been proposed in the literature as an alternative for digital circuits taking advantage the fact that any Boolean function could be implemented with the same cell, just configuring external signals, this work shows a methodology that could be followed particularly for the design of a four bits logic gate, using the so-called neuron MOS transistor (ν-MOS). Simulation results show the feasibility of the design for performing as XNOR, NOR, OR, XOR, AND or NAND logic gates, for instance. In order to extrapolate the design to a higher number of bits, the key issue is to properly consider the weight of the input capacitances in correlation with the number of input bits. A D/A converter can be used as the input stage of the configuration. This design considers the D/A converter-less version, since it helps to increase device integration as the number of transistors used is reduced with no difference in its performance. The design should be based on the theoretical floating potential diagram (FPD) of the desired logic gate.

An interconnected type-1 fuzzy algorithm for impulsive noise cancellation in multicarrier-based power line communication systems

This paper introduces an interconnected type-1 fuzzy algorithm which is trained by a modified version of the Scaled Conjugated Gradient method for impulsive noise cancellation in discrete multitone/orthogonal frequency-division multiplexing (DMT/OFDM)-based systems for broadband power line communications. The advanced algorithm makes use of the fuzzy systems capacity of dealing with uncertainties to reduce the presence of high-power impulsive noises while the DMT/OFDM technique copes with the severe intersymbol interference observed in power line channels. As a result, for a given error probability, a high number of bits can be allotted to each subchannel due to the signal-to-noise ratio enhancements achieved by the proposed fuzzy algorithm. The simulation results show that the novel fuzzy algorithm not only achieve a high data rate, but it also outperforms the standard impulsive noises techniques and other computational intelligence-based techniques, especially in the presence of additive and high-power impulsive noises.