Higher Number Of Bits Research Articles

Impulse Noise Mitigation Based on Computational Intelligence for Improved Bit Rate in PLC-DMT

This paper introduces a modified version of the discrete multi-tone transceiver (DMT) to increase the data rate in broadband power-line communications (PLC). Basically, a computational-intelligence technique trained by a second-order optimization method is applied to mitigate the high-power impulse noise, while the DMT copes with the severe intersymbol interference observed in power-line channels. The masking of the impulse noise enhances the signal-to-noise ratio in each DMT subchannel. As a result, a high number of bits can be allotted to each subchannel for a given error probability. The simulation results reveal that the proposed PLC-DMT solution outperforms, in terms of the data rate, traditional PLC-DMT over different environments, especially in the presence of additive high-power impulse noise.

Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits

The efficient implementation of adders in differential logic can be carried out using a new generate signal (N) presented in this paper. This signal enables iterative shared transistor structures to be built with a better speed/area performance than a conventional implementation. It also allows adders developed in domino logic to be easily adapted to differential logic. Based on this signal, three 32-b adders in differential cascode switch voltage (DCVS) logic with completion circuit for applications in self-timed circuits have been fabricated in a standard 1.0-/spl mu/m two-level metal CMOS technology. The adders are: a ripple-carry (RC) adder, a carry look-ahead (CLA) adder, and a binary carry look-ahead (BCL) adder. The RC adder has the best levels of performance for random input data, but its delay is significantly influenced by the length of the carry propagation path, and thus is not recommended in circuits with nonrandom input operands. The BCL adder is the fastest but has a high cost in chip area. The CLA adder provides an intermediate option, with an area which is 20% greater than that of the RC adder. Its average delay is slightly greater than that of the other two adders, with an addition time which increases slowly with the carry propagate length even for adders with a high number of bits.

A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBTs, MESFETs, and Si BJTs. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2 Gb/s 1:8 demultiplexer are described. These multigigabit LSIs have been achieved mainly by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (f/sub max/), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSIs are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding. >