Higher Chip Density Research Articles

M.2 NVMe SSD의 신뢰성 향상을 위한 히트싱크 열 설계

M.2 NVMe SSD (Non-Volatile Memory express Solid-State Drive), which have higher computational speed and reliability than conventional devices, have come to be widely used. Recent studies have reported that M.2 NVMe SSD are beginning to have thermal issues due to the increasing heat generation occurring with the high chip density and high-performance operation in a limited space. Thermal issues in the controller and memory units of M.2 NVMe SSD lead to increased failure rates and decreased data retention times. In this study, we propose a compact and optimized thermal solution for commercial M.2 NVMe SSD installed between the mainboard and GPU (Graphic Processing Unit). A thermal and fluid dynamics simulation of an M.2 NVMe SSD, including the heatsink, was performed, and the Genetic Algorithm method was used to optimize the heatsink size.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Nanoelectromechanical (NEM) Devices for Logic and Memory Applications

Recent research on NEM devices for logic and memory applications has been reviewed from the perspective of monolithic 3D (M3D) heterogeneous integration. In addition, the backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are described in detail. Moreover, 65-nm process based M3D CMOS-NEM RL circuits were proposed. It is predicted that proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.

Integrated ultra-high-performance graphene optical modulator

Abstract With the increasing need for large volumes of data processing, transport, and storage, optimizing the trade-off between high-speed and energy consumption in today’s optoelectronic devices is getting increasingly difficult. Heterogeneous material integration into silicon- and nitride-based photonics has showed high-speed promise, albeit at the expense of millimeter-to centimeter-scale footprints. The hunt for an electro-optic modulator that combines high speed, energy efficiency, and compactness to support high component density on-chip continues. Using a double-layer graphene optical modulator integrated on a Silicon photonics platform, we are able to achieve 60 GHz speed (3 dB roll-off), micrometer compactness, and efficiency of 2.25 fJ/bit in this paper. The electro-optic response is boosted further by a vertical distributed-Bragg-reflector cavity, which reduces the driving voltage by about 40 times while maintaining a sufficient modulation depth (5.2 dB/V). Modulators that are small, efficient, and quick allow high photonic chip density and performance, which is critical for signal processing, sensor platforms, and analog- and neuromorphic photonic processors.

Photosensitive Complementary Inverters Composed of n‐Channel ReS2 and p‐Channel Single‐Walled Carbon Nanotube Field‐Effect Transistors

For robustness on security and ultralow power consumption for Internet of Things (IoT) sensors, including ultraminiaturization for high chip density, 2D multilayered ReS2 field‐effect transistors (FETs) combined with photoinsensitive single‐walled carbon nanotube (SWNT) FETs are demonstrated for application in light‐to‐frequency (LTF) conversion circuits. Herein, multilayered ReS2 FETs with a direct bandgap (≈1.5 eV) have discernible photoresponsivity of ≈17 A W−1 for red and ≈128 A W−1 for green, respectively, with photodetectivity (≈109 Jones), leading to excellent operation for photosensitive inverters, partly associated with the photoinsensitive SWNT FETs for p‐channel devices. Moreover, the electrical parameters for photosensitive complementary inverters, according to different wavelengths in the dark and under, red (λR = 660 nm), green (λG = 530 nm), and blue (λB = 450 nm) light, are experimentally extracted, and their SPICE simulation‐based validation on working principles of ring oscillators (ROs) is confirmed under light illumination. More impressively, ultralow power consumption for the proposed scheme is achieved due to both the direct bandgap and the large‐energy bandgap, as compared with conventional multilayered MoS2 FET‐based photosensitive inverters, rationally validating the promising opportunity for applications in the envisioned IoT sensor systems.

Island-Style Monolithic Three-Dimensional CMOS-Nanoelectromechanical Logic Circuits

Island-style monolithic three-dimensional (M3D) CMOS- nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated showing the full operation of the island-style RL: single-tile and tile-to-tile operation. For the fabrication of M3D CMOS-NEM RL circuits, 65-nm CMOS baseline process was used, in which copper NEM memory switches are integrated over the CMOS logic circuits by using dual damascene process. It is predicted that our proposed M3D CMOS-NEM RL circuits will exhibit $4.6 \times$ higher chip density, $2.3 \times$ higher operation frequency and $9.3 \times$ lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.

Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part II: Design Guidelines for Device, Array, and Architecture

Using the reduced resistor network developed in Part I of this two-part article, we present practical design guidelines from device to architecture levels to achieve ultrahigh-density 3-D vertical resistive switching memory (VRSM). We first design both hexagon and comb arrays using 7-nm FinFET as pillar driving transistors (pillar drivers). Small-footprint pillar drivers are necessary for a high pillar areal density competitive to 3-D NAND. We then organize the arrays into an architecture using the compact staircase and highly conductive wordplane connection (WPC) to maximize array efficiency and chip density. We investigate the memory and selector requirements, tolerance of parasitic resistances, latency, and energy consumption for both hexagon and comb architectures. The results indicate that the hexagon array with large low-resistance state (LRS) and nonlinearity (NL) is required for ultradense 3-D VRSM. Compared to the comb array, the hexagon array benefits from a continuous WP pattern and yields a better tolerance of parasitic resistances and a smaller latency. The energy consumptions of both architectures are similar. Compared to the most advanced 3-D NAND, 3-D VRSM has higher chip density and shows better potential for future ultradense storage.

Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints

In order to support the pad-limited application-specific integrated circuit (ASIC) designs, the flip chip package is used and provides the highest chip density compared to other packaging technologies. In this paper, we propose the first work of peripheral-input and -output (I/O) free-assignment flip-chip routing considering practical bump pad and I/O pad constraints and flexibilities. Unlike previous studies regarding all nets as the same, we differentiate signal and power/ground nets and set different bump pad assignment constraints for substrate layout optimization. In our flow, a global routing-based I/O-bump assignment algorithm is proposed with a multicommodity flow network model. Afterward, two detailed routing algorithms minimizing the total wirelength are presented. Finally, a dynamic programming (DP)-based I/O pad planning technique is applied to further reduce the number of wire bends. Experimental results based on modified industrial cases show that our algorithm flow not only achieves 100% routability of all testcases but also minimizes total wirelength, total wire bends, and bump utilization.

Power Optimized Programmable Embedded Controller Using Icg

In this proposed work I have design and implemented 8 bit microcontroller using intelligent clock gating to optimize the power of PEC.power optimization is a key factor in high integrated vlsi chip.The increasing prominence of portable systems and need to limit power consumption (and hence, heat dissipation) in very high density VLSI chips have led to rapid and innovative development in low power design during the recent years . The driving forces behind these developments are portable device application requiring low power dissipation and high throughput, such as notebook computers . Portable communication device, and personal \digital assistants (PDAs) . In most of these cases , the requirements for low power consumption must be met along with equally demanding goals of high chip density and high throughput. Hence, low power design of digital integrated circuits has emerged as a very active and rapidly developing field. Clock gating is a well- understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires that the designers add a small amount of logic to their RTL code to disable or deselect unnecessarily active sequential elements registers. Results shows that ICG is very effective in power optimizationof PEM as it reduces power by adding small amount of logic to their RTL code to disable or deselect unnecessarily active sequential elements registers.TheVerilog code for all the modules is written in a hierarchical fashion starting with the smallest units and progressively, building upon them to develop the entire structure. Simulation of the entire FPGA is done to verify the functionality following which, synthesis and design implementation is carried out.

Novel Current Driving Circuit for Active Matrix Organic Light Emitting Diode

This paper describes a novel current driving circuit for an active matrix organic light emitting diode (AMOLED). The proposed current driving circuit has a lower power consumption and higher chip density for the AMOLED display compared with the conventional one because all elements operate at a normal voltage and are shielded from the high voltage of the panel. The chip size and power consumption of the current driving circuit for an AMOLED can be improved by about 30 to 40% and 10 to 20%, respectively, compared with the conventional one.