Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints

Abstract

In order to support the pad-limited application-specific integrated circuit (ASIC) designs, the flip chip package is used and provides the highest chip density compared to other packaging technologies. In this paper, we propose the first work of peripheral-input and -output (I/O) free-assignment flip-chip routing considering practical bump pad and I/O pad constraints and flexibilities. Unlike previous studies regarding all nets as the same, we differentiate signal and power/ground nets and set different bump pad assignment constraints for substrate layout optimization. In our flow, a global routing-based I/O-bump assignment algorithm is proposed with a multicommodity flow network model. Afterward, two detailed routing algorithms minimizing the total wirelength are presented. Finally, a dynamic programming (DP)-based I/O pad planning technique is applied to further reduce the number of wire bends. Experimental results based on modified industrial cases show that our algorithm flow not only achieves 100% routability of all testcases but also minimizes total wirelength, total wire bends, and bump utilization.