Recently, two-dimensional transition metal dichalcogenides (2D TMDCs) have been researched as promising channel materials for filed effect transistors (FETs) owing to their high mobility at atomic-level thickness. As miniaturization and high performance of the electronic devices are required, however, high contact resistance at the interface between the metal electrode and 2D TMDC channel has become a major challenge.1 The high contact resistance at the metal-semiconductor interface originates from the uncontrollable high Schottky barrier height (SBH). Due to Fermi-level pinning induced by metal-induced gap state (MIGS) and defect-induced gap state (DIGS), the barrier height cannot be controlled by conventional Schottky-Mott rule, regardless of metal work function. Since MIGS occurs due to perturbation of metal wave function into the semiconductor, inserting semimetallic material as contact layer can be a solution to suppress the MIGS and further reduce the contact resistance.2 In this study, ALD TiS2 was used as semimetallic contact layer between the MoS2 channel and Ti/Au electrode for MoS2-based TFT. With the TiS2 contact layer, we could observe improvements in overall device performances, which is attributed to the semimetallic nature of TiS2. In addition, low temperature ALD TiS2 process contributed to the clean interface with vdW bonding between MoS2 and TiS2, resulting in suppression of DIGS, as well as MIGS. Owing to the ALD TiS2 contact, we could mitigate FLP and achieve metal-semiconductor interface with low Schottky barrier height, resulting in low contact resistance. References 1 K. Schauble et al., “Uncovering the effects of metal contacts on monolayer MoS2,” ACS Nano, vol. 14, no. 11, pp. 14798–14808, 2020, doi: 10.1021/acsnano.0c03515. 2 P. C. Shen et al., “Ultralow contact resistance between semimetal and monolayer semiconductors,” Nature, vol. 593, no. 7858, pp. 211–217, 2021, doi: 10.1038/s41586-021-03472-9.
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