High-voltage LDMOS Transistors Research Articles

A New Technique for Improving Kink Effect in High-Voltage LDMOS Transistors: M-shape Drift Region

A New Technique for Improving Kink Effect in High-Voltage LDMOS Transistors: M-shape Drift Region

High-Voltage LDMOS Transistors on an SOI Structure for Electronics That Operate in Extreme Conditions

The parameters of high-voltage LDMOS transistors on a silicon structure on an insulator formed in a technological cycle combined with the manufacturing technology of low-voltage CMOS LSI are investigated. LDMOS transistors are studied under conditions of the temperature changing in the range –60 to 300°C and exposure to ionizing radiation.

ESD robustness concern and optimization for high-voltage p-type LDMOS transistor with thin gate oxide used as the output driver

The p-type lateral double-diffused MOS (pLDMOS) transistor with thin gate oxide has significant advantages when being used as a high side output driver in high-voltage ICs (HVICs), because it usually possesses larger current density compared with a device with thick gate oxide. However, in order to reduce the chip size, many HVICs do not have specialized output electrostatic discharge (ESD) protection cells, so the pLDMOS device is operated both as the output driver and the ESD protection structure. In this work, we have found that the ESD robustness of the pLDMOS with thin gate oxide is poor. As a result, this device is risky for those area-efficient HVICs. To solve the contradiction, the inner mechanism of the poor ESD robustness for the pLDMOS with thin gate oxide has been investigated. Moreover, an improved method, by adjusting the overlap length between the special p-well and the source p+ implantation region, has been presented. The experimental results show that the ESD robustness of the improved pLDMOS with thin gate oxide has been obviously increased, while the large current density can be also maintained.

Substrate current characterization and optimization of high voltage LDMOS transistors

A 30-V LDMOS integrated with a standard 0.15μm CMOS process is investigated for its double-hump substrate current (Ib) characteristics. The origin of this abnormal second substrate current hump is explained by Kirk effect. The impact of this second hump of Ib on reliability and device performance is observed. An analytical expression for the second hump of Ib is established by calculating the impact ionization in the drift region according to the electric field distribution obtained by solving Poisson’s equation. The calculated results are compared against the silicon data under various gate/drain bias voltages showing excellent consistency. Additionally, based on the derived expressions for substrate current, the process parameters are optimized achieving much lower substrate current and better reliability performance.

A Surface-Potential-Based High-Voltage Compact LDMOS Transistor Model

In this paper, a surface potential-based compact model is described for high-voltage LDMOS transistors. This model combines the low-voltage MOS region with the high-voltage drift region of an LDMOS transistor. The model includes the effect of the gate extending over the drift region as well as its temperature behavior and geometry scaling. In contrast to subcircuit models, the model has no internal node, since the so-called internal drain voltage is explicitly expressed in terms of the external terminal voltages. By use of an explicit formulation of the surface potential, the dc model thus combines the benefits of short computation times and robustness with accuracy. A comparison with dc measurements shows that the dc model provides an accurate description in all regimes of operation, ranging from subthreshold to super-threshold. In addition, a nodal charge model is derived, to account for the time-dependent behavior of the device. Capacitances obtained from high-frequency measurements show a good agreement with those obtained from the nodal charge model.

Small-signal and power evaluation of novel BiCMOS-compatible short-channel LDMOS technology

We describe a very short-channel 0.15-/spl mu/m LDMOS transistor with a breakdown voltage of up to 60 V, manufactured in a standard 0.35-/spl mu/m BiCMOS process. At 1900 MHz and a 12-V supply voltage, the 0.4-mm-gatewidth device with shortest drain drift region gives 100-mW output power P/sub 1dB/ at a drain efficiency of 43%. It has a transducer power gain of over 20 dB. The maximum current gain cutoff frequency f/sub T/ is 15 GHz, and the maximum available gain cutoff frequency f/sub MAX/ is 38 GHz. We show the dependence of f/sub T/, an f/sub MAX/ of gate and drain bias for transistors with different drain drift region length. The LDMOS process module does not affect the performance or the models of other devices. We present for the first time a simple way to create high-voltage high-performance LDMOS transistors for an RF power amplifier use even in a very downscaled silicon technology.

Sub-Circuit Based SPICE Model for High Voltage LDMOS Transistors

High voltage lateral DMOS transistors are very difficult to model due to the complex structure. As a result of complexity and the range of variation in transistor structure no general LDMOS model exists. Standard SPICE models of MOSFETs, JFETs together with a resistor have been used in the sub-circuit model. Self-heating effects have been included in a specially design unit. The model shows good overall accuracy.