High Voltage Device Structure Research Articles

Substrate-bias effect on the breakdown characteristic in a new silicon high-voltage device structure

A novel silicon double-RESURF LDMOS structure with an improved breakdown characteristic by substrate bias technology (SB) is reported. The P-type epitaxial layer is embedded between an N-type drift region and an N-type substrate to block the conduction path in the off-state and change the distributions of the bulk electric field. The substrate bias strengthens the charge share effect of the drift region near the source, and the vertical electric field peak under the drain is decreased, which is especially helpful in improving the vertical breakdown voltage in a lateral power device with a thin drift region. The numerical results by MEDICI indicate that the breakdown voltage of the proposed device is increased by 97% compared with a conventional LDMOS, while maintaining a lowon-resistance.

A novel high-voltage device structure with an N+ ring in substrate and the breakdown voltage model

A novel high-voltage device structure with a floating heavily doped N+ ring embedded in the substrate is reported, which is called FR LDMOS. When the N+ ring is introduced in the device substrate, the electric field peak of the main junction is reduced due to the transfer of the voltage from the main junction to the N+ ring junction, and the vertical breakdown characteristic is improved significantly. Based on the Poisson equation of cylindrical coordinates, a breakdown voltage model is developed. The numerical results indicate that the breakdown voltage of the proposed device is increased by 56% in comparison to conventional LDMOS.

Complementary charge islands structure for a high voltage device of partial-SOI

A new partial-SOI (PSOI) high voltage device structure named CNCI PSOI (complementary n+-charge islands PSOI) is proposed. CNCI PSOI is characterized by equidistant high concentration n+-regions on the top and bottom interfaces of a dielectric buried layer of a PSOI device. When a high voltage is applied to the device, complementary holes and electron islands are formed on the two n+-regions on the top and bottom interfaces, therefore effectively enhancing the electric field of the dielectric buried layer (EI) and increasing the breakdown voltage (BV), alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CNCI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. BV and EI of the CNCI PSOI LDMOS increase to 591 V and 512 V/μm from 216 V and 81.4 V/μm of the conventional PSOI with a lower SHE, respectively. The influence of structure parameters on the device characteristics is analyzed for the proposed device in detail.

A new SOI high voltage device based on E-SIMOX substrate

A new NI (n+ charge islands) high voltage device structure based on E-SIMOX (epitaxy-the separation by implantation of oxygen) substrate is proposed. It is characterized by equidistant high concentration n+-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field (EV) are located in the spacing of two neighboring n+-regions on the interface by the force from lateral electric field (EL) and the compositive operation of Coulomb's forces with the ionized donors in the undepleted n+-regions. This effectively enhances the electric field of dielectric buried layer (EI) and increases breakdown voltage (VB). An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology (E-SIMOX).

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n+-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n+-regions on the interface by the force with ionized donors in the undepleted n+-regions, and therefore effectively enhance the electric field of the dielectric buried layer (E1) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E1 of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.

Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bg</sub> , resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bg</sub> only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 V/mum of the conventional SOI to 457 V/mum at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bg</sub> = 0 V, leading to a high BV. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO.

A Novel 700-V SOI LDMOS With Double-Sided Trench

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A novel silicon-on-insulator (SOI) high-voltage device structure with double-sided trenches on the buried oxide layer (DT SOI) is proposed and its breakdown characteristics are investigated theoretically and experimentally in this letter. Theoretically, the charges implemented in the DTs, whose density changes with the drain voltage, increase the electric field in the buried layer and modulate the electric field in the drift region, which results in the enhancement of the breakdown voltage (BV). Experimentally, the BV of 730 V is obtained for the first time in SOI LDMOS with DT on 20-<formula formulatype="inline"><tex>$\mu\hbox{m}$</tex></formula> SOI layer and 1- <formula formulatype="inline"><tex>$\mu\hbox{m}$</tex></formula> buried oxide layer. </para>

A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable- k dielectric buried layer

A new SOI high voltage device structure with variable- k (permittivity) dielectric buried layer (VK SOI) is proposed in this paper. In this structure, the buried layer is made of two dielectrics, one of which is the low- k dielectric. The breakdown voltage is enhanced due to the modulation effect of the variable- k buried layer on the electric fields in the buried layer and drift region. An analytical model for the electric field and breakdown voltage in VK SOI is presented taking the modulation effect into account, from which the RESURF condition is derived. The dependences of the electric field distribution and breakdown voltage on the device parameters for VK SOI are investigated. Compared with the conventional SOI, the electric field of the buried layer and breakdown voltage of VK SOI with relative permittivity k I2 = 2 of the low- k dielectric are enhanced by 81% and 56%, respectively. The analytical results are in good agreement with those of 2D simulations. Finally, the proposed model and RESURF condition can be well applied to the conventional SOI and also extended to VT SOI (variable thickness buried layer SOI) devices.

A note on trap recombination in high voltage device structures

The carrier lifetime is a very important parameter influencing all important characteristics of bipolar devices both discrete and integrated structures and carrier lifetime tailoring is an important part of power semiconductor device technology. In presented paper, recombination through traps (centres with a deep energy level between edge of bandgap and Fermi level) is discussed in more details. It has been shown that some traps can considerably influence recombination rate in silicon and that at some traps a considerable temperature dependence of the centre cross-sections may be found. This is demonstrated in the case of iridium traps with a deep energy level 0.28 eV below the conduction band which capture cross-section temperature dependence has been found σ p+ σ n∝ T −6.5. Further, the problem on low injection carrier lifetime in low-doped layers of high voltage semiconductor devices is also discussed.

Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film

Studies of high-voltage lateral device structures on a thin silicon layer over silicon dioxide have been carried out. It was found both theoretically and experimentally that over 600-V devices can be realized using a structure consisting of an n diffusion layer over a 15- mu m-thick high-resistivity n/sup -/ silicon layer over 3- mu m silicon dioxide (SOI). A method is presented to enhance breakdown voltage by applying a large share of the voltage to the bottom oxide. >

A new expression for breakdown voltage of practical linearly graded p-n junction

An analytical investigation of realistic linearly graded silicon p-n junctions, currently used in high-voltage device structures, is performed. Basic corrections to the fundamental theory of reverse-biased, linearly graded p-n junctions are analytically formulated. Closed-form relations for the breakdown voltage BV and peak space-charge region extension (at breakdown) in practical linearly graded junctions are presented. A thorough investigation of linearly graded junctions used in power devices is performed. Basic corrections to the fundamental theory of linearly graded junctions have been analytically formulated. It is shown that the departure from the classical linearly graded case is more obvious as the background impurity concentration drops below C/sub B/=10/sup 15/ cm/sup -3/ and the impurity gradient a increases above 5*10/sup 16/ cm/sup -4/. For C/sub B/ 10/sup 16/ cm/sup -4/, the linearly graded junction behaves like an abrupt one. For a>10/sup 19/ cm/sup -4/ and C/sub B/ >

Modeling and characterization of CMOS-compatible high-voltage device structures

The design, implementation, and modeling of high-voltage MOS transistors in a Standard CMOS technology is described. High voltage n- and p-channel transistors, with breakdown voltages of 50 and 180 V, respectively, have been fabricated. A SPICE-compatible model for these transistors is described, and its accuracy verified by comparison with experimental results.