High Density Of Threading Dislocations Research Articles

Microstructure and reflectance of porous GaN distributed Bragg reflectors on silicon substrates

Distributed Bragg reflectors (DBRs) based on alternating layers of porous and non-porous GaN have previously been fabricated at the wafer-scale in heteroepitaxial GaN layers grown on sapphire substrates. Porosification is achieved via the electrochemical etching of highly Si-doped layers, and the etchant accesses the n+-GaN layers through nanoscale channels arising at threading dislocations that are ubiquitous in the heteroepitaxial growth process. Here, we show that the same process applies to GaN multilayer structures grown on silicon substrates. The reflectance of the resulting DBRs depends on the voltage at which the porosification process is carried out. Etching at higher voltages yields higher porosities. However, while an increase in porosity is theoretically expected to lead to peak reflectance, in practice, the highest reflectance is achieved at a moderate etching voltage because etching at higher voltages leads to pore formation in the nominally non-porous layers, pore coarsening in the porous layers, and in the worst cases layer collapse. We also find that at the high threading dislocation densities present in these samples, not all dislocations participate in the etching process at low and moderate etching voltages. However, the number of dislocations involved in the process increases with etching voltage.

Ion implantation induced nucleation and epitaxial growth of high-quality AlN

AlN materials have a wide range of applications in the fields of optoelectronic, power electronic, and radio frequency. However, the significant lattice mismatch and thermal mismatch between heteroepitaxial AlN and its substrate lead to a high threading dislocation (TD) density, thereby degrading the performance of device. In this work, we introduce a novel, cost-effective, and stable approach to epitaxially growing AlN. We inject different doses of nitrogen ions into nano patterned sapphire substrates, and then deposit the AlN layers by using metal-organic chemical vapor deposition. Ultraviolet light-emitting diode (UV-LED) with a luminescence wavelength of 395 nm is fabricated on it, and the optoelectronic properties are evaluated. Compared with the sample prepared by the traditional method, the sample injected with N ions at a dose of 1×10<sup>13</sup> cm<sup>–2</sup> exhibits an 82% reduction in screw TD density, the lowest surface roughness, and a 52% increase in photoluminescence intensity. It can be seen that appropriate dose of N ion implantation can promote the lateral growth and merging process in AlN heteroepitaxy. This is due to the fact that the process of implantation of N ions can suppress the tilt and twist of the nucleation islands, effectively reducing the density of TDs in AlN. Furthermore, in comparison with the controlled LED, the LED prepared on the high quality AlN template increases 63.8% and 61.7% in light output power and wall plug efficiency, respectively. The observed enhancement in device performance is attributed to the TD density of the epitaxial layer decreasing, which effectively reduces the nonradiative recombination centers. In summary, this study indicates that the ion implantation can significantly improve the quality of epitaxial AlN, thereby facilitating the development of high-performance AlN-based UV-LEDs.

Investigation of the Impact of Point Defects in InGaN/GaN Quantum Wells with High Dislocation Densities.

In this work, we report on the efficiency of single InGaN/GaN quantum wells (QWs) grown on thin (<1 µm) GaN buffer layers on silicon (111) substrates exhibiting very high threading dislocation (TD) densities. Despite this high defect density, we show that QW emission efficiency significantly increases upon the insertion of an In-containing underlayer, whose role is to prevent the introduction of point defects during the growth of InGaN QWs. Hence, we demonstrate that point defects play a key role in limiting InGaN QW efficiency, even in samples where their density (2-3 × 109 cm-2) is much lower than that of TD (2-3 × 1010 cm-2). Time-resolved photoluminescence and cathodoluminescence studies confirm the prevalence of point defects over TDs in QW efficiency. Interestingly, TD terminations lead to the formation of independent domains for carriers, thanks to V-pits and step bunching phenomena.

8.1 μ m-emitting InP-based quantum cascade laser grown on Si by metalorganic chemical vapor deposition

This study presents the growth and characterization of an 8.1 μm-emitting, InGaAs/AlInAs/InP-based quantum cascade laser (QCL) formed on an InP-on-Si composite template by metalorganic chemical vapor deposition (MOCVD). First, for the composite-template formation, a GaAs buffer layer was grown by solid-source molecular-beam epitaxy on a commercial (001) GaP/Si substrate, thus forming a GaAs/GaP/Si template. Next, an InP metamorphic buffer layer (MBL) structure was grown atop the GaAs/GaP/Si template by MOCVD, followed by the MOCVD growth of the full QCL structure. The top-surface morphology of the GaAs/GaP/Si template before and after the InP MBL growth was assessed via atomic force microscopy, over a 100 μm2 area, and no antiphase domains were found. The average threading dislocation density (TDD) for the GaAs/GaP/Si template was found to be ∼1 × 109 cm−2, with a slightly lower defect density of ∼7.9 × 108 cm−2 after the InP MBL growth. The lasing performance of the QCL structure grown on Si was compared to that of its counterpart grown on InP native substrate and found to be quite similar. That is, the threshold-current density of the QCL on Si, for deep-etched ridge-guide devices with uncoated facets, is somewhat lower than that for its counterpart on native InP substrate, 1.50 vs 1.92 kA/cm2, while the maximum output power per facet is 1.64 vs 1.47 W. These results further demonstrate the resilience of QCLs to relatively high residual TDD values.

Reverse Leakage Mechanism of Dislocation-Free GaN Vertical p-n Diodes

The reverse leakage mechanism of threading dislocation (TD)-free gallium nitride (GaN) vertical p-n diode was investigated in various temperature range, and it was compared with that of the p-n diode having a threading dislocation density (TDD) of around 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . The reverse leakage current was increased markedly by increasing the temperature from 400 K, the dominant mechanism was explained by thermionic and Poole-Frenkel emissions for TD-free and high-TDD p-n diodes, respectively. At high temperatures and electric fields, the leakage current of the high TDD p-n diode showed 2 times higher than the TD-free p-n diode. These results indicate that the performance of vertical GaN devices, especially when employed at high temperatures and electric fields, can be enhanced by removing TDs.

Low Dark Current Operation in InAs/GaAs(111)A Infrared Photodetectors: Role of Misfit Dislocations at the Interface.

We demonstrate an extended short-wave infrared (e-SWIR) photodetector composed of an InAs/GaAs(111)A heterostructure with interface misfit dislocations. The layer structure of the photodetector consists simply of an n-InAs optical absorption layer directly grown with a thin undoped-GaAs spacer layer on n-GaAs by molecular beam epitaxy. The lattice mismatch was abruptly relaxed by forming a misfit dislocation network at the initial stage of the InAs growth. We found high-density threading dislocations (1.5 × 109 cm-2) in the InAs layer. The current-voltage characteristics of the photodetector at 77 K had a very low dark current density (<1 × 10-9 A cm-2) at a positive applied voltage (electrons flow from n-GaAs to n-InAs) of up to ∼+1 V. Simulation of the band structure revealed that the direct connection of GaAs and InAs and the formation of interfacial states by the misfit dislocations play significant positive roles in suppressing dark current. Under illumination with e-SWIR light at 77 K, a clear photocurrent signal was observed with a 2.6 μm cutoff wavelength, which is consistent with the bandgap of InAs. We also demonstrated e-SWIR detection at room temperature with a 3.2 μm cutoff wavelength. The maximum detectivity at 294 K exceeds 2 × 108 cm Hz0.5 W-1 for the detection of e-SWIR light at 2 μm.

Terrace Engineering of the Buffer Layer: Laying the Foundation of Thick GaN Drift Layer on Si Substrates

AbstractVertical GaN‐on‐Si devices are promising for the next‐generation high‐voltage power electronics with low cost and high efficiency. However, their applications are impeded by the limited thickness of crack‐free GaN layers and high threading dislocation density (TDD) in the layer. Buffer layers are crucial for stress control while they usually behave with poor surface morphology, which causes early stress relaxation in GaN and limited thickness. Hereby, a terrace engineering approach for the buffer layers is proposed. Through tuning the supersaturation ratio, the terrace width can be manipulated and an atomically smooth AlGaN buffer layer can be realized, which effectively reduces the compressive stress relaxation and provides a firm foundation for thick GaN growth. As a result, a 7.5 µm thick GaN drift layer with TDD as low as 8.6 × 107 cm−2 is achieved on Si substrates. The room temperature electron mobility of the GaN drift layer can be raised up to 1210 cm2 V−1 s−1. The fabricated PiN diode shows a high breakdown voltage of 1058 V as well as a high on/off ratio of 1012. This work thus truly demonstrates the potential of high‐performance and low‐cost GaN‐based electronic as well as optoelectronic devices on Si platforms.

GaAs/Si Tandem Solar Cells with an Optically Transparent InAlAs/GaAs Strained Layer Superlattices Dislocation Filter Layer

Epitaxial growth of III–V materials on Si is a promising approach for large-scale, relatively low-cost, and high-efficiency Si-based multi-junction solar cells. Several micron-thick III–V compositionally graded buffers are typically grown to reduce the high threading dislocation density that arises due to the lattice mismatch between III–V and Si. Here, we show that optically transparent n-In0.1Al0.9As/n-GaAs strained layer superlattice dislocation filter layers can be used to reduce the threading dislocation density in the GaAs buffer on Si while maintaining the GaAs buffer thickness below 2 μm. Electron channeling contrast imaging measurements on the 2 μm n-GaAs/Si template revealed a threading dislocation density of 6 × 107 cm−2 owing to the effective n-In0.1Al0.9As/n-GaAs superlattice filter layers. Our GaAs/Si tandem cell showed an open-circuit voltage of 1.28 V, Si bottom cell limited short-circuit current of 7.2 mA/cm2, and an efficiency of 7.5%. This result paves the way toward monolithically integrated triple-junction solar cells on Si substrates.

Room-temperature nonradiative recombination lifetimes in c-plane Al1−xInxN epilayers nearly and modestly lattice-matched to GaN (0.11 ≤ x ≤ 0.21)

Lattice-matched Al1−xInxN / GaN heterostructures with InN mole fraction (x) of 0.18 have attracted considerable interest for use in GaN-based optoelectronic devices. Because the light emission efficiency (ηemission) of Al1−xInxN alloys is far less than that of InxGa1−xN, understanding its causes is essential. For this purpose, room-temperature photoluminescence lifetime (τPLRT), which almost represents the nonradiative recombination lifetime that limits the internal quantum efficiency in low ηemission semiconductors, of c-plane Al1−xInxN epilayers nearly and modestly lattice-matched to GaN (0.11≤x≤0.21) was examined. For the epilayers grown on low threading dislocation density (TDD) GaN substrates (≪107cm−2), τPLRT principally decreased with increasing x, indicating a progressive increase in the concentration of nonradiative recombination centers (NRCs), NNRC. One of the probable causes is the growth temperature (Tg) reduction that is indispensable to incorporate more In, because in insufficient Tg regime higher Tg is preferred for enhancing the surface migration of adatoms to decrease the concentrations of vacancies that compose NRCs. The Al1−xInxN epilayers of the same x but grown on high TDD (&amp;gt;108cm−2) GaN-on-sapphire templates exhibited shorter τPLRT. Because the diffusion length of minority carriers was nearly zero in the Al1−xInxN epilayers, the shorter τPLRT indicates higher bulk NNRC in high TDD epilayers. The Al1−xInxN epilayers of considerably rough surface morphologies exhibited spatially inhomogeneous τPLRT, implying that excited carriers recombined everywhere at InN-rich to InN-poor portions, where NNRC were likely lower to higher, respectively, than the average due to the deviations in the surface stoichiometry at various non-c-plane surfaces at a given Tg.

Defect Engineering in MBE-Grown CdTe Buffer Layers on GaAs (211)B Substrates

Demand for high-performance HgCdTe infrared detectors with larger array size and lower cost has fuelled the heteroepitaxial growth of HgCdTe on CdTe buffer layers on lattice-mismatched alternative substrates such as Si, Ge, GaAs and GaSb. However, the resulting high threading dislocation (TD) density in HgCdTe/CdTe limits their ultimate application. Herein, strained CdZnTe/CdTe superlattice layers have been used as dislocation filtering layers (DFL) to reduce the TDs in CdTe buffer layers grown on GaAs (211)B substrates (14.4% lattice-mismatch) by molecular beam epitaxy (MBE). Cross-sectional microstructure characterization indicates that the DFLs suppress the propagation of TDs. For optimal Zn content combined with thermal annealing, the DFLs effectively reduce the defect density of the upper-most CdTe layer from low-107 cm−2 to the critical level of below 106 cm−2. In comparison to conventional buffer CdTe layers, the in-plane lattice of the CdTe layers in/near the DFL region is compressively strained, leading to a spread in x-ray double-crystal rocking curve full-width at half-maximum values but better in-plane lattice-matching with HgCdTe. The combined advantages of lower dislocation density and better lattice-matching with HgCdTe indicate that the DFL approach is a promising path towards achieving heteroepitaxy of high-quality HgCdTe on large-area lattice-mismatched substrates for fabricating next-generation infrared detectors.

Reduced Dislocation Density of an InP/GaAs Virtual Substrate Grown by Metalorganic Chemical Vapor Deposition

Integrating indium phosphide (InP) material on a gallium arsenide (GaAs) substrate to form an InP/GaAs virtual substrate has been an attractive research subject over the past decade. However, the epitaxial growth of InP on GaAs is challenging due to a large mismatch in the lattice constant and thermal expansion coefficient. This paper describes the successful hetero-epitaxy of InP on a GaAs substrate by metalorganic chemical vapor deposition. The hetero-epitaxy in this study utilized a hybrid growth method involving a thin indium gallium arsenide (InGaAs) linearly graded buffer, two-step InP growth, and a post-annealing process. Transmission electron microscopic observations showed that a traditional two-step InP/GaAs virtual substrate was smooth but had a high threading dislocation density (TDD) of 1.5 × 109 cm−2 near the InP surface. The high TDD value can be reduced to 2.3 × 108 cm−2 by growing the two-step InP on a thin InGaAs linearly graded buffer. The TDD of an InP/GaAs virtual substrate can be further improved to the value of 1.5 × 107 cm−2 by removing the low-temperature InP nucleation layer and carrying out a post-annealing process. A possible reason for the improvement in TDD may relate to a dislocation interaction such as the annihilation of mobile threading dislocations. Room-temperature photoluminescence spectra of InP/GaAs virtual substrates with different TDD values were compared in this study. The optical and micro-structural characterization results suggest that the proposed growth method may be feasible for making good-quality and relatively low-cost InP/GaAs virtual substrates for the integration of optoelectronic devices on them.

Sensitivity of indium molar fraction in InGaN quantum wells for near-UV light-emitting diodes

InGaN-based quantum wells (QWs) have higher threading dislocation density (TDD) in InGaN Light-emitting diode (LED). Despite of higher TDD, variation of Indium (In) molar fraction in the QW generate localized excitons with higher Indium composition, thus preventing bound carriers from non-radiative recombination. In this work, the sensitivity of the Indium molar fraction in InGaN QWs is explored for near-ultraviolet (UV) LEDs. The theoretically calculated results show that as the Indium composition increases in InGaN QWs, the radiative recombination increases along with an increase in carrier injection efficiency. The reduced non-radiative recombination for higher Indium composition leads to the enhanced spontaneous emission rate and internal quantum efficiency (IQE). For lowered Indium composition, the peak emission wavelength of the InGaN LEDs shift toward the shorter wavelength and the performances degrade drastically. Hence for shorter UV LEDs, the AlGaN-based device structure should be a suitable choice.

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon.

Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.

Invalidation of the acquisition of internal quantum efficiency using temperature-dependent photoluminescence in InGaN quantum wells with high threading dislocation density

Temperature-dependent photoluminescence (TDPL) is mostly employed to evaluate the internal quantum efficiency (IQE) of light-emitting semiconductors. The key assumption of this method is that the IQE is 100% under low temperature (LT) (e.g. 10 K), which is often considered to be reasonable without any verification. This may lead to an obvious contradiction between a considerable IQE value and poor emission intensity, especially when there exists a high threading dislocation density. In this paper, the power-dependent photoluminescence (PDPL), TDPL, and time-resolved photoluminescence are carried out on three InGaN single-quantum-well samples with diverse threading dislocation densities to obtain the IQE and the recombination coefficients. It is found that the IQE at LT must be confirmed by PDPL and used to calibrate the TDPL values. Then, the IQEs obtained from different measurements are in good agreement under the same excitation conditions. A phenomenological model is proposed to explain the evolution of IQE and recombination coefficients with threading dislocation density. This work indicates that the commonly used TDPL is not reliable, as the hypothesis of negligible nonradiative recombination at LT is proven to not be valid for InGaN quantum well samples, especially those with high threading dislocation density (>1010 cm−2).

Laser-induced activation of Mg-doped GaN: quantitative characterization and analysis

We investigate the effectiveness of laser-induced treatment as compared to rapid-thermal annealing (RTA) for the activation of p-type dopant in Mg-doped GaN layers. The study is based on a wide set of analytical techniques, including resistivity measurements, atomic force microscopy (AFM), scanning emission microscopy, dynamic secondary ion mass spectroscopy (SIMS), time-of-flight (TOF) SIMS and energy dispersive x-ray (EDX) spectroscopy in combination with scanning transmission electron microscopy (STEM). Samples are treated at different energy densities and in different atmospheres, to provide a comprehensive overview of the topic. The analysis is carried out on GaN-on-Si samples, to demonstrate the effectiveness of the treatment even in presence of high threading dislocation densities. The original results presented in this paper indicate that: (a) laser treatment is an effective process for activating the p-type dopant in Mg-doped GaN layers; even at low irradiation energy densities (400 mJ cm−2) the laser treatment can effectively activate the Mg doping, with the best resistivity results obtained (around 1.5 Ωcm) comparable with those obtained by optimized RTA; (b) resistivity varies with temperature with activation energy E a = 0.14 eV, which is compatible with the MgGa acceptor in GaN; (c) TOF-SIMS, AFM, EDX-STEM analysis indicates that the laser treatment does not modify the concentration profile of magnesium and surface roughness for low and moderate laser energy densities; changes are detected only for energy densities above 600 mJ cm−2, for which a significant degradation of the surface is revealed. The experimental evidence collected within this paper provide an accurate assessment of the process conditions for effective laser activation of Mg-doped GaN, thus allowing the fine-tuning required for selective activation and for industrial applications.

Challenges of relaxed n-type GaP on Si and strategies to enable low threading dislocation density

We directly show that doping type strongly affects the threading dislocation density (TDD) of relaxed GaP on Si, with n-type GaP having a TDD of ∼3.1 × 107 cm−2, nearly 30× higher than both p-type and unintentionally doped GaP at ∼1.1 × 106 cm−2. Such a high TDD is undesirable since n-GaP on Si serves as the starting point for the growth of epitaxial III-V/Si multi-junction solar cells. After highlighting additional challenges for highly n-doped GaP on Si including increased surface roughness, anisotropic strain relaxation, and inhomogeneous TDD distributions from blocking of the dislocation glide, we go on to show that the TDD of n-GaP on Si rises by 10× as the doping concentration increases from ∼5 × 1016 to ∼2 × 1018 cm−3. Next, we investigate the effects of additional dopant choices on the TDD, determining that electronic effects dominate over solute effects on the dislocation velocity at these concentrations. Finally, we demonstrate the respective roles of compressively strained superlattices, low-temperature initiation, and lowered n-type doping concentration on reducing the TDD for n-GaP on Si. By combining all three, we attain relaxed n-GaP on Si with a TDD of 1.54(±0.20) × 106 cm−2, approaching parity with p-GaP on Si. Such high-quality n-GaP on Si will play an important role in boosting the efficiency of epitaxial III-V/Si multi-junction solar cells.

Growth of InAs0.32Sb0.68 on GaAs using a thin GaInSb buffer and strain superlattice layers

We report on the growth of an InAs0.32Sb0.68 layer on (001) GaAs substrates. The lattice mismatch strain between the InAs0.32Sb0.68 layer and the GaAs substrate was accommodated using a thin 50–100 nm Ga0.35In0.65Sb buffer with interfacial misfit (IMF) dislocations. The epitaxial structures were characterized using transmission electron microscopy and x-ray diffraction analysis. The threading dislocation density in the InAs0.32Sb0.68 layer was reduced successfully to ∼1 × 108 cm−2 using the combination of a Ga0.35In0.65Sb IMF buffer and InSb/Ga0.35In0.65Sb superlattice layers. Compared to GaSb/GaAs and InSb/GaAs interfaces, a significantly higher threading dislocation density (&amp;gt;1011 cm−2) was observed at the Ga0.35In0.65Sb/GaAs interface. Detailed analysis suggests that high threading dislocation density in the Ga0.35In0.65Sb IMF buffer could be due to the non-uniform microscopic distribution of indium and gallium atoms. This work is beneficial to the scientific community in the growth of the InAs0.32Sb0.68 material as it provides a novel approach to prepare a platform for the growth of the InAs0.32Sb0.68 material, which does not have a suitable lattice-matched substrate, on the widely available GaAs substrate.

Thinned GaInP/GaInAs/Ge solar cells grown with reduced cracking on Ge|Si virtual substrates

Reducing the formation of cracks during growth of GaInP/GaInAs/Ge 3-junction solar cells on Ge|Si virtual substrates has been attempted by thinning the structure, namely the Ge bottom cell and the GaInAs middle cell. The theoretical analysis performed using realistic device parameters indicates that the GaInAs middle cell can be drastically thinned to 1000 nm while increasing its In content to 8% with an efficiency loss in the 3-junction cell below 3%. The experimental results show that the formation of macroscopic cracks is prevented in thinned GaInAs/Ge 2-junction and GaInP/GaInAs/Ge 3-junction cells. These prototype crack-free multijunction cells demonstrate the concept and were used to rule out any possible component integration issue. The performance metrics are limited by the high threading dislocation density over 2·107cm−2 in the virtual substrates used, but an almost current matched, crack-free, thinned 3-junction solar cell is demonstrated, and the pathway towards solar cells with higher voltages identified.

Defect-insensitive current–voltage characteristics of Schottky barrier diode formed on heteroepitaxial α-Ga2O3 grown by mist chemical vapor deposition

An n-type α-Ga2O3 layer was grown by mist chemical vapor deposition on a sapphire substrate, and a Ti/α-Ga2O3 Schottky barrier diode was fabricated. Although the α-Ga2O3 layer has a high threading dislocation density (larger than 109 cm−2), the ideality factor of 1.03 was obtained from the forward current–voltage characteristic in the range of 298 K–423 K, indicating the clear thermionic emission transport. The reverse current–voltage characteristic was also investigated, and the leakage current showed good agreement with the theoretical calculation based on the thermionic field emission model without any fitting parameter in the temperature range of 298 K–423 K.

Threading Dislocation Reduction of Ge by Introducing a SiGe/Ge Superlattice

Ge growth on Si is essential e.g. for photonics device integration (e.g. Ge photodiode) into Si based CMOS platform (1). However, due to 4.2% of lattice mismatch between Ge and Si, misfit dislocations (MD) and threading dislocations (TD) are introduced for strain relaxation after exceeding critical thickness. In order to realize low-darkcurrent Ge photodiode, improvement of crystallinity is important. High quality Ge growth techniques by combining various annealing techniques (at 800~850oC) are reported (2-3). However, because of low melting point of Ge (937oC), the Ge growth process is typically integrated at the last part of front-end process. Therefore, these annealing processes are affecting device parameters of existing devices. In previous paper, we reported Ge/SiGe superlattice (SL) fabrication and found improvement of TD density (TDD) by increasing Si composition of SiGe in the SL (4). Here we report TDD improvement of Ge by introducing the SL without annealing.Ge growth with SiGe/Ge SL is carried out using reduced pressure chemical vapor deposition system. Si(100) wafers are used. After an HF last cleaning, the wafer is loaded into reactor and baked at 1000oC and cooled down to 600oC in H2 and further cooled down to 350oC in N2. After that 100 nm-thick seed Ge is deposited using N2-GeH4 gas. Then the wafer is heated up to 500oC in H2 and Ge/SiGe superlattice is fabricated using H2-GeH4 and H2-SiH4-GeH4 gases, respectively. Furthermore, 2.8 µm thick Ge is deposited at 550oC using H2-GeH4 gas.Thickness is measured by cross section SEM and spectroscopic ellipsometry. TDD is determined by Secco defect etching technique. Strain and relaxation of Ge and SiGe layers are measured by XRD reciprocal space mapping. Distribution of the MD and the TD are measured by cross section TEM.In the case of direct Ge growth on Si (Fig. 1a), MDs are formed at interface between Ge and Si. TDs are spreading into the Ge layer. Some of the TDs are long and extending to surface. These MD and TD formations are due to the lattice mismatch between Ge and Si. On the other hand, in the case of Ge sample grown on ×20 Si0.3Ge0.7 / Ge SL (Fig. 1b), most of MDs are formed at interface between 100 nm-thick Ge buffer and Si substrate. Additionally high density of TDs are observed in the Ge buffer and the SL layer. In the SL layer, lower TDD is observed in the upper part compared to that in the deeper part. At the interface between upper 2.8 µm thick Ge and the SL layer, MD and high density of TDs toward lateral direction is observed indicating relaxation. TDD in the 2.8 µm thick Ge layer seems to be lower compared to that in Fig. 1a).In the case of direct Ge growth on Si, TDD of ~7.5×108 cm-2 is obtained (Fig. 2). The TDD is comparable to previously reported results (2). By depositing 2.8 µm thick Ge on Si0.2Ge0.8 SL, TDD is decreased to ~5.4×108 cm-2. With decreasing Ge concentration of SiGe layer of the SL, decrease of TDD is observed until 40%. However, by replacing SiGe layers to mono-layers of Si, increased TDD is observed, which might be due to too high strain at interface between Si and SiGe.Figure 3 shows TDD of 2.8 µm thick Ge deposited on Si0.2Ge0.8/Ge SL with different Si0.2Ge0.8 and Ge thickness combination without changing periodicity of the SL. Lower TDD is observed when the 2.8 µm thick Ge is deposited on the SL with higher Si0.2Ge0.8 thickness. Possible reason is higher degree of relaxation of the SL layer.In Fig. 4, TDD of 2.8 µm thick Ge deposited on SLs of various lattice parameters are shown. By reducing lateral lattice parameter of the SiGe/Ge SL by increasing SiGe thickness or Si concentration, TDD decreases. The reduction of the TDD is fitting to one line for both cases. These results indicate that higher plastic relaxation of the SL occurs on the Ge buffer due to increased compressive strain of SiGe in the SL, and the TDD reduction of the Ge on the SL may be caused by similar mechanism of reverse graded buffer. By introducing SiGe/Ge SL, multiple effect of the reverse graded buffer may be expected. Reference (1) S. Lischke et al. Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) , (2014) 29(2) Y. Yamamoto et al Solid-State Electron. 60 (2011) 2(3) Y. Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007(4) Y. Yamamoto et al. Jpn. J. Appl. Phys. 59, SGGK10 (2020) Figure 1