High Temperature Storage Life Research Articles

Reliability Assessment and Activation Energy Study of Au and Pd-Coated Cu Wires Post High Temperature Aging in Nanoscale Semiconductor Packaging

Wearout reliability and high temperature storage life (HTSL) activation energy of Au and Pd-coated Cu (PdCu) ball bonds are useful technical information for Cu wire deployment in nanoscale semiconductor device packaging. This paper discusses the influence of wire type on the wearout reliability performance of Au and PdCu wire used in fine pitch BGA package after HTSL stress at various aging temperatures. Failure analysis has been conducted to identify the failure mechanism after HTSL wearout conditions for Au and PdCu ball bonds. Apparent activation energies (Eaa) of both wire types are investigated after HTSL test at 150 °C, 175 °C and 200 °C aging temperatures. Arrhenius plot has been plotted for each ball bond types and the calculated Eaa of PdCu ball bond is 0.85 eV and 1.10 eV for Au ball bond in 110 nm semiconductor device. Obviously Au ball bond is identified with faster IMC formation rate with IMC Kirkendall voiding while PdCu wire exhibits equivalent wearout and or better wearout reliability margin compare to conventional Au wirebond. Lognormal plots have been established and its mean to failure (t50) have been discussed in this paper.

Extended reliability of gold and copper ball bonds in microelectronic packaging

Wire bonding is the predominant mode of interconnection in microelectronic packaging. Gold wire bonding has been refined again and again to retain control of interconnect technology due to its ease of workability and years of reliability data. Copper (Cu) wire bonding is well known for its advantages such as cost-effectiveness and better electrical conductivity in microelectronic packaging. However, extended reliabilities of Cu wire bonding are still unknown as of now. Extended reliabilities of Au and Pd-coated Cu (Cu) ball bonds are useful technical information for Au and Cu wire deployment in microelectronic packaging. This paper discusses the influence of wire type and mold compound effect on the package reliability and after several component reliability stress tests. Failure analysis has been conducted to identify its associated failure mechanisms after the package conditions for Au and Cu ball bonds. Extended reliabilities of both wire types are investigated after unbiased HAST (UHAST), temperature cycling (TC), and high-temperature storage life test (HTSL) at 150, 175, and 200 °C aging temperatures. Weibull plots have been plotted for each reliability stress. Obviously, Au ball bond is found with longer time to failure in unbiased HAST stress compared to Cu ball bonds for both mold compounds. Cu wire exhibits equivalent package and or better reliability margin compared to Au ball bonds in TC and HTSL tests. Failure mechanisms of UHAST and TC have been proposed, and its mean time to failure (t 50), characteristic life (t 63.2, η), and shape parameter (s) have been discussed in this paper. Feasibility of silver (Ag) wire bonding deployment in microelectronic packaging is discussed at the last section in this paper.

Reliability assessment and mechanical characterization of Cu and Au ball bonds in BGA package

Extended reliability and mechanical characterisation of Au and Pd-coated Cu (Cu) ball bonds are useful technical information for Au and Cu wire deployment in semiconductor device packaging. This paper discusses the influence of wire type on the package reliability and mechanical performance after several component reliability stress tests. Failure analysis has been conducted to identify the associated failure mechanisms of Au and Cu ball bonds after reliability tests. Wire pull strength and ball bond shear (with its break modes) of both wire types are investigated after unbiased highly accelerated temperature and humidity stress test (UHAST), temperature cycling (TC) and high temperature storage life test (HTSL) at various aging temperatures. Reliability Weibull plots have been plotted for each reliability stresses. Obviously Au ball bond is found with longer time-to-failure in Unbiased HAST stress compare to Cu ball bonds. Cu wire exhibits equivalent package and or better reliability margin compare to Au ball bonds in TC and HTSL tests. Failure mechanisms of UHAST and HTSL have been proposed and its mean-time-to failure (t50), characteristics life (t63.2, η) and shape parameter (s) have been discussed in this paper.

Wearout Reliability and Intermetallic Compound Diffusion Kinetics of Au and PdCu Wires Used in Nanoscale Device Packaging

Wearout reliability and diffusion kinetics of Au and Pd‐coated Cu (PdCu) ball bonds are useful technical information for Cu wire deployment in nanoscale semiconductor device packaging. This paper discusses the HAST (with bias) and UHAST (unbiased HAST) wearout reliability performance of Au and PdCu wires used in fine pitch BGA packages. In‐depth failure analysis has been carried out to identify the failure mechanism under various wearout conditions. Intermetallic compound (IMC) diffusion constants and apparent activation energies (Eaa) of both wire types were investigated after high temperature storage life test (HTSL). Au bonds were identified to have faster IMC formation, compared to slower IMC growth of PdCu. PdCu wire was found to exhibit equivalent or better wearout reliability margin compared to conventional Au wire bonds. Failure mechanisms of Au, Cu ball bonds post‐HAST and UHAST tests are been proposed, and both Au and PdCu IMC diffusion kinetics and their characteristics are discussed in this paper.

Highly Reliable and Manufacturable Ultrafine Pitch Cu–Cu Interconnections for Chip-Last Embedding With Chip-First Benefits

Flip-chip packaging of Ultrafine pitch integrated circuits aggravates the stress-strain concerns as the interconnection pitch is decreased, requiring a fundamentally different system approach to interconnections, underfill processes and interfaces, and the substrate. This paper demonstrates an innovative and manufacturable solution to achieve excellent reliability at Ultrafine pitch (~30 μm) using direct copper-copper (Cu-Cu) interconnections with adhesives. A number of 30-μm bump pitch test vehicles (TVs) were designed with 3 mm × 3 mm chips to extract both daisy chain resistance and single-bump resistance data. Assembled bump resistivity was found to be ~ 3-4× lower than most solders. Performance of these TVs was studied for high temperature storage (HTS) life test, unbiased-highly accelerated stress test (U-HAST) and thermal cycling test (TCT). Test results showed that the assemblies with this next generation interconnection technology depicted excellent reliability results in HTS, U-HAST, and TCT tests. Based on these results, it is concluded that adhesive materials, provide unique opportunities for Ultrafine pitch and high performance interconnections.

Adhesion and Evaluation of Thermoplastic Nonconductive Film Materials in Flip Chip for Fine-Pitch Chip-on-Flex

In this paper, flip-chip interconnections were made on very flexible polyethylene naphthalate substrates using nonconductive films (NCFs). In general, the NCF/underfill materials are both epoxy thermosetting substances, and it was found that the curing process would increase the internal stress, shrinkage, and warpage. Therefore, the use of thermalplastic materials might solve these problems. Such materials provide lower water absorption at 0.56 ± 0.05% and curing for 4 h at 150 ± 10°C for the elimination of voids. The chip-on-flex (COF) parameters are a bonding temperature of 400 ± 10°C, a bonding force of 95 ± 5 N, and a bonding time of 0.4 ± 0.1 s. The workability test shows that the Au/Sn eutectic condition has fine adhesion for leads and bumps, and the bond accuracy is controlled in less than one-third bump space. The COF products were able to pass all the reliability tests, including the highly accelerated stress, high-temperature storage life, low-temperature storage life, temperature cycling, and pressure cooker tests. The results indicate that the COF assemblies exhibit fine performance in the reliability, workability, and simulation tests. Thus, the NCF thermoplastic materials are suitable for replacing thermosetting materials, and can be applied in fine pitch to improve the reliability issues associated with COF products.

Evaluation of Electrical Characteristics of the Copper Metallized SPDT GaAs Switches at Elevated Temperatures

Copper-metallized AlGaAs/InGaAs pseudomophic high-electron mobility transistor single-pole-double-throw (SPDT) switches utilizing platinum (Pt, 70 nm) as the diffusion barrier have been studied and demonstrated. As compared with the Au-metallized switches, the Cu-metallized SPDT switches exhibited comparable performance with insertion loss less than 0.5 dB, return loss larger than 20 dB, isolation larger than 35 dB, and the input power for 1-dB compression (input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> ) of 28.3 dBm at 2.5 GHz. In order to evaluate the temperature- dependent impact on dc and RF characteristics of the copper- metallized switches for high-temperature applications, the switches have been tested at different temperatures. The device exhibits low thermal threshold coefficients (deltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> /deltaT) of - 0.25 mV/K from 300 K to 500 K, good microwave performance at 380 K with insertion loss less than 0.5 dB, isolation higher than 40 dB, and the input power for 1-dB compression (input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> ) of 28.45 dBm at 2.5 GHz. To test the thermal stability of the Pt diffusion barrier, these switches were annealed at 250degC for 20 h. After the annealing, the switches showed no degradation of the dc characteristics. In addition, after a high temperature storage life environment test at 150degC, these copper-metallized switches remained capable of excellent power handling. To test the operation reliability of the copper-metallized switches, the copper-metallized switches were subjected to ON/OFF (control voltage = +3/0 V exchange) stress test for 24 h at room temperature. The devices maintained excellent RF characteristics after the stress test. Consequently, it is successfully demonstrated through these tests that copper metallization using Pt as the diffusion barrier could be applied to the GaAs monolithic microwave integrated circuit switch fabrication with good RF performance, high-temperature characteristics, and reliability.

Evaluation of Electrical Characteristics of the Copper-Metallized SPDT GaAs Switches at Elevated Temperatures

Copper-metallized AlGaAs/InGaAs pseudomophic high-electron mobility transistor single-pole-double-throw (SPDT) switches utilizing platinum (Pt, 70 nm) as the diffusion barrier have been studied and demonstrated. As compared with the Au-metallized switches, the Cu-metallized SPDT switches exhibited comparable performance with insertion loss less than 0.5 dB, return loss larger than 20 dB, isolation larger than 35 dB, and the input power for 1-dB compression (input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> ) of 28.3 dBm at 2.5 GHz. In order to evaluate the temperature- dependent impact on dc and RF characteristics of the copper- metallized switches for high-temperature applications, the switches have been tested at different temperatures. The device exhibits low thermal threshold coefficients (deltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> /deltaT) of - 0.25 mV/K from 300 K to 500 K, good microwave performance at 380 K with insertion loss less than 0.5 dB, isolation higher than 40 dB, and the input power for 1-dB compression (input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> ) of 28.45 dBm at 2.5 GHz. To test the thermal stability of the Pt diffusion barrier, these switches were annealed at 250degC for 20 h. After the annealing, the switches showed no degradation of the dc characteristics. In addition, after a high temperature storage life environment test at 150degC, these copper-metallized switches remained capable of excellent power handling. To test the operation reliability of the copper-metallized switches, the copper-metallized switches were subjected to ON/OFF (control voltage = +3/0 V exchange) stress test for 24 h at room temperature. The devices maintained excellent RF characteristics after the stress test. Consequently, it is successfully demonstrated through these tests that copper metallization using Pt as the diffusion barrier could be applied to the GaAs monolithic microwave integrated circuit switch fabrication with good RF performance, high-temperature characteristics, and reliability.

SPDT GaAs Switches With Copper Metallized Interconnects

Copper metallized AlGaAs/InGaAs pseudomorphic high-electron-mobility transistor (PHEMT) single-pole-double-throw (SPDT) switches utilizing platinum (Pt, 70nm) as the diffusion barrier is reported for the first time. In comparison with the Au metallized switches, the Cu metallized SPDT switches exhibited comparable performance with insertion loss of less than 0.5dB, isolation larger than 35dB and the input power for one dB compression (input P1dB ) of 27dBm at 2.5GHz. These switches were annealed at 250deg for 20h for thermal stability test and showed no degradation of the dc characteristics after the annealing. Also, after 144h of high temperature storage life (HTSL) environment test, these switches still remained excellent and reliable radio frequency (RF) characteristics. It is successfully demonstrated for the first time that the copper metallization using Pt as the diffusion barrier could be applied to the GaAs monolithic microwave integrated circuits switch fabrication with good RF performance and reliability

Comparative analysis of RF LDMOS capacitance reliability under accelerated ageing tests

This paper presents the results of comparative reliability study of C– V characteristics through three accelerated ageing tests for stress applied to an RF LDMOS: Thermal shock tests (TST, air–air test), thermal cycling tests (TCT, air–air test) and high temperature storage life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The investigation findings of electrical parameter degradations after various ageing tests are discussed. Feedback capacitance (Crs) is reduced by 16% and gate–drain capacitance (Cgd) by 42%. This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. A physical simulation software has been used to confirm qualitatively degradation phenomena.

Numerical and experimental correlation of high temperature reliability of gold wire bonding to intermetallics (Au/Al) uniformity

A study of the Au/Al intermetallics compound (IMC) in gold wire bonds on aluminum pads is presented. A test vehicle has been deliberately built for high temperature storage (HTS) test. There are two kinds of samples, i.e., one is with uniform intermetallics in the ball bond at time zero, and another one is with non-uniform intermetallics. It is found that the package with initial uniform intermetallics passed the HTS test, while the package with initial non-uniform intermetallics failed with ball lift failure after HTS storage. Unique thermo-mechanical simulation is performed to understand the failure mechanism for HTS. Two types of intermetallics model have been established correspondingly, i.e., one with uniform intermetallics and another one with non-uniform intermetallics. The volume-induced stress under HTS has been simulated. It is found that the difference between IMC stresses in uniform and non-uniform models is not obvious, while there is a large difference between stresses in gold area of uniform and non-uniform model. For the non-uniform model, high normal tensile stress exists in the inner convex areas of gold bond, which connect two pieces of separate intermetallics, while for the uniform model, there is no such high stress area. The interfaces between Au and IMC in non-uniform model are the critical interfaces with high stress. It is indicated from these results that HTS life is much longer for the bond with uniform IMC than that with non-uniform IMC. The thermo-mechanical stress model correlates well with the test results.

Comparative analysis of accelerated ageing effects on power RF LDMOS reliability

We present in this paper results of comparative reliability study of three accelerated ageing tests applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test), Thermal Cycling Tests (TCT, air-air test) and High Temperature Storage Life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The results obtained show the variation and the Device’s performance quantitative shifts for some macroscopic electric parameters such as threshold voltage (V th), transconductance (G m), drain-source current (I ds), on-state resistance (R ds_on) and feedback capacitance (C rs) under various ageing tests. To understand the degradation phenomena that appear after ageing, we used a new electro-thermal model implemented in Agilent’s ADS as a reliability tool.

Material characterization and in-situ process monitoring for a robust ACF base flip chip technology

Thermal and mechanical material properties involved in ACF base flip chip technology were carefully investigated. A process sequence was designed based on thermal and mechanical properties of ACFs and substrates determined with thermo-mechanical analysis equipment, dynamic mechanical analysis equipment and differential scanning calorimeter measurements. In-situ monitoring of contact resistance of two single interconnects, daisy chain resistance, bonding force and bonding temperature was performed. Monitoring interconnect resistance and daisy chain resistance, bonding forces of 10 or 20 kg/die were adapted. Extra force applied to junctions caused bump, pad and substrate deformation, resulting in poor junction reliability. It will be shown that in-situ process monitoring can be a powerful tool for process optimization and material selection for ACF base flip chip technology. Interconnect reliability of ACF base flip chip technology was evaluated under several accelerated stress conditions. It was found that ACF interconnect is very stable up to 2 000 h under high temperature storage life test at 125/spl deg/C and temperature and humidity test at 85/spl deg/C and 85% RH, regardless of bump materials, ACF materials and substrate materials examined in this work. This work demonstrated that a careful study of ACF thermal and mechanical properties and in-situ monitoring of ACF flip chip process can provide a robust ACF flip chip technology.

Question marks to the extrapolation to lower temperatures in high temperature storage life (HTSL) testing in plastic encapsulated IC'S

A model has been constructed to describe ball-bond corrosion in HTSL stress testing. In this model ion-mobility has been believed to be the rate determining step and has been found to be non-linear for the anti-popcorn plastic. In HTSL testing an Arrhenius type extrapolation of the mean-time to failure (MTTF) at high temperature has been used, to predict the value at lower temperatures. This method proves to be correct for a low-stress plastic. However possibly it underestimates the value for an anti-popcorn plastic based on ion conductivity data. Strikingly, below the Tg of the anti-popcorn plastic, the reaction rates estimated from the ion conductivity data are the same for both the low-stress and the anti-popcorn plastic encapsulants.

A mechanism of threshold voltage changes for WN x gate GaAs MESFETs in high temperature storage life tests

Reliability of 0.8 μm WN x gate GaAs MESFETs with a self-aligned lightly doped drain structure has been investigated by means of high temperature storage life tests at 250, 275 and 300 °C. The observed reduction in threshold voltage followed by drain current increase was just reverse in contrast to those for ‘gate sinking’ effect reported on several Au-based gates. The correlation of the threshold voltage reduction with Shottky barrier height and other MESFET parameter changes during the tests suggested a model related to the short channel effect for the threshold voltage reduction, which was proved true by submitting samples of gate lengths 0.7, 1.0 and 1.5 μm to high temperature storage life tests. The dependence of threshold voltage changes on gate orientation relative to the crystal axis was also evaluated with 1.0 μm gate MESFETs to investigate the model in more detail. MESFETs parallel to [001] axis showed minimum absolute threshold voltage changes, while those parallel to piezoelectrically active [011] and [0 1 1] axes showed decreasing and increasing threshold voltage changes, respectively. From these results, the threshold voltage changes were tentatively ascribed to the relief of the stress caused by poly-imide die bonding process for packaging MESFET chips. In other words, WN x gate GaAs MESFET chips themselves were concluded to show no appreciable degradation up to 1000 hr storage life tests at 250 and 275 °C, except for ohmic contact degradation at 300 °C.

Reliability of Postmolded IC Packages

This paper discusses the current reliability issues involved with typical postmolded IC packages. Four major topics are presented, namely, stress, moisture permeation and corrosion-related problems, adhesion, and outgassing impurities. As the trend moves toward higher lead count, with increasingly larger dies which require more power dissipation within smaller package outlines, stress reduction will become a main concern. Methods to quantify package stresses in situ are outlined, together with the advantages and drawbacks of various schemes for decoupling the silicon die from the molding compound. Since the typical molding compound is permeable to moisture, the package collects water during stringent qualification tests (autoclave, T/H, and HAST), and even under normal ambient conditions. Any ionic impurities in the molding compound will combine with the absorbed water to form an electrolytic pool. This increases the likelihood of corrosion in the presence of passivation defects or exposed metal lines. Device structures designed to follow moisture permeation and detect water-induced damage are discussed. The integrity of the interface between the molding compound and the device components is crucial to the long term reliability of the package. Delamination at the die interface produces complex stress profiles that can result in various defects ranging from metal line shift, passivation cracking, corner die chipping, to ball bond fatigue. Poor adhesion along the leads also opens potential paths for moisture ingress. The effects of assembly conditions and various adhesion enhancing schemes on the package integrity are evaluated. Finally, outgassing of halogenated (bromine and antimony oxide) byproducts added for flame retardancy during high temperature storage life testing results in ball bond degradation. The interaction yields typically porous intermetallic structures which grow in size with exposure time, leading ultimately to bond lifting. Possible reaction mechanisms are presented.