High-temperature Power Electronics Applications Research Articles

Ga2O3/NiO junction barrier Schottky diodes with ultra-low barrier TiN contact

Power Schottky barrier diodes (SBDs) face an inherent trade-off between forward conduction loss and reverse blocking capability. This limitation becomes more severe for ultra-wide bandgap (UWBG) SBDs due to the large junction field. A high Schottky barrier is usually required to suppress the reverse leakage current at the price of an increased forward voltage drop (VF). This work demonstrates a Ga2O3 junction barrier Schottky (JBS) diode that employs the embedded p-type NiO grids to move the peak electric field away from the Schottky junction, thereby allowing for the use of an ultra-low barrier TiN Schottky contact. This JBS diode concurrently realizes a low VF of 0.91 V (at forward current of 100 A/cm2) and a high breakdown voltage over 1 kV, with the VF being the lowest in all the reported vertical UWBG power diodes. Based on the device characteristics measured up to 200 °C, we further analyze the power loss of this JBS diode across a wide range of operational duty cycles and temperatures, which is found to outperform the TiN/Ga2O3 SBDs or NiO/Ga2O3 PN diodes. These findings underscore the potential of low-barrier UWBG JBS diodes for high-frequency, high-temperature power electronics applications.

The advantages and short circuit characteristics of SiC MOSFETs

SiC MOSFETs have exhibited considerable benefits in high-frequency, high-voltage, and high-temperature power electronics applications with outstanding material attributes as a result of the rapid advancement of power electronics technology. SiC MOSFETs slower short-circuit tolerance and faster switching rates provide new issues for the short-circuit prevention technology. In the opening section of the study, Si and SiC MOSFETs are compared and evaluated using various models and parametric factors. It has been demonstrated that SiC MOSFETs outperform Si MOSFETs in a variety of conditions and applications. The many SiC MOSFET short-circuit failure types as well as their underlying theories are initially explained in the papers main body. In addition, it examines the fundamentals of short-circuit test procedures and SiC MOSFET test circuits. The issues and limitations of the currently available SiC MOSFET short-circuit protection technology are then explored, along with factors impacting the short-circuit of SiC MOSFETs that are thoroughly examined. Lastly, the SiC MOSFET short-circuit protection technology development trend is forecasted, and potential future areas for improvement and innovation are considered. SiC MOSFET short-circuit protection technology will be enhanced and optimized to satisfy the needs of efficient and dependable power electronic systems as technology advances and application requirements expand.

Aging investigation of the latest standard dual power modules using improved interconnect technologies by power cycling test

The latest standard “New Dual” power module has been developed for both silicon and silicon-carbide devices to meet the increasing demands in high reliability and high temperature power electronic applications. Due to the new package is just starting to release on the market, the reliability performance has not been fully studied. This paper investigates the power cycling capabilities of a 1.7 kV/1.8 kA IGBT power module based on the new package. Both the electrical and thermal performances have been studied before and after the power cycling. Neither the chips nor bond wires have noticeable degradation after 1.2 million cycles with ΔTj = 100 K and Tjmax = 150 °C. Nevertheless, the end-of-life criterion of an increased conduction voltage (Vce) in the test environment has been reached at about 600 k cycles. The further scanning acoustic microscopy test unveils that the fatigue site shifts from the conventional near-to-die interconnect (e.g., bond wire lift-offs) to the direct bond copper (DBC) substrate and baseplate layers. Considering the new package has more than ten times cycle life than the traditional power module, it expects the thermo-mechanical fatigue is not the life-limiting mechanism with further improved interconnect technologies. Meanwhile, as the previous bottlenecks (e.g., bond wires) are addressed, some new fatigue mechanisms, e.g., delamination of the DBC, become visible in this new package.

Al1-xScxN Thin Films at High Temperatures: Sc-Dependent Instability and Anomalous Thermal Expansion.

Ferroelectric thin films of wurtzite-type aluminum scandium nitride (Al1−xScxN) are promising candidates for non-volatile memory applications and high-temperature sensors due to their outstanding functional and thermal stability exceeding most other ferroelectric thin film materials. In this work, the thermal expansion along with the temperature stability and its interrelated effects have been investigated for Al1−xScxN thin films on sapphire Al2O3(0001) with Sc concentrations x (x = 0, 0.09, 0.23, 0.32, 0.40) using in situ X-ray diffraction analyses up to 1100 °C. The selected Al1−xScxN thin films were grown with epitaxial and fiber textured microstructures of high crystal quality, dependent on the choice of growth template, e.g., epitaxial on Al2O3(0001) and fiber texture on Mo(110)/AlN(0001)/Si(100). The presented studies expose an anomalous regime of thermal expansion at high temperatures >~600 °C, which is described as an isotropic expansion of a and c lattice parameters during annealing. The collected high-temperature data suggest differentiation of the observed thermal expansion behavior into defect-coupled intrinsic and oxygen-impurity-coupled extrinsic contributions. In our hypothesis, intrinsic effects are denoted to the thermal activation, migration and curing of defect structures in the material, whereas extrinsic effects describe the interaction of available oxygen species with these activated defect structures. Their interaction is the dominant process at high temperatures >800 °C resulting in the stabilization of larger modifications of the unit cell parameters than under exclusion of oxygen. The described phenomena are relevant for manufacturing and operation of new Al1−xScxN-based devices, e.g., in the fields of high-temperature resistant memory or power electronic applications.

High-temperature stability of Ni-Sn intermetallic joints for power device packaging

In this study, the feasibility and high-temperature stability of Ni-Sn bonded joints fabricated by transient liquid phase sintering (TLPS) were investigated for high-temperature power electronics applications. A 30Ni-70Sn (wt%) TLPS paste was fabricated with micro-sized pure Ni and Sn powders, and chip bonding was performed on a direct bonded copper (DBC) substrate. During TLPS bonding, Sn particles melted and reacted with Ni particles, which resulting in the formation of stable Ni-Sn TLPS intermetallic joints. During aging treatments at 150 and 200 °C, the formed Ni3Sn4 phases were transformed into the Ni3Sn2. With increasing aging treatments, the reactions between Ni3Sn4 intermetallics and remaining Ni particles increased, which resulted in the formation of the Ni-rich Ni-Sn intermetallics. Even after 1000 h at an aging temperature of 200 °C, there is no significant difference in the stable and dense microstructure of Ni-Sn TLPS joints. In addition, their mechanical strengths did not vary significantly even after long-term treatment for 1000 h at 150 and 200 °C. This means that the Ni-Sn TLPS joints have a good long-term microstructural stability and mechanical reliability at high temperatures up to 200 °C. Therefore, we conclude that the Ni-Sn paste is a promising candidate as a die-attach material for high-temperature electronic assemblies.

Microstructure evolution and shear strength of full Cu3Sn- microporous copper composite joint by thermo-compression bonding

Purpose The purpose of this paper is to quickly manufacture full Cu3Sn-microporous copper composite joints for high-temperature power electronics applications and study the microstructure evolution and the shear strength of Cu3Sn at different bonding times. Design/methodology/approach In this paper, a novel structure of Cu/composite solder sheet/Cu was designed. The composite solder sheet was made of microporous copper filled with Sn. The composite joint was bonded by thermo-compression bonding under pressure of 0.6 MPa at 300°C. The microstructure evolution and the growth behavior of Cu3Sn at different bonding times were observed by electron microscope and metallographic microscope. The shear strength of the joint was measured by shear machine. Findings At initial bonding stage the copper atoms in the substrate and the copper atoms in the microporous copper dissolved into the liquid Sn. Then the scallop-liked Cu6Sn5 phases formed at the interface of liquid Sn/microporous copper and liquid Sn/Cu substrates. During the liquid Sn changing to Cu6Sn5 phases, Cu3Sn phases formed and grew at the interface of Cu6Sn5/Cu substrates and Cu6Sn5/microporous copper. After that the Cu3Sn phases continued to grow and the Cu3Sn-microporous copper composite joint with a thickness of 100 µm was successfully obtained. The growth rule of Cu3Sn was parabolic growth. The shear strength of the composite joints was about 155 MPa. Originality/value This paper presents a novel full Cu3Sn-microporous copper composite joint with high shear strength for high-temperature applications based on transient liquid phase bonding. The microstructure evolution and the growth behavior of Cu3Sn in the composite joints were studied. The shear strength and the fracture mechanism of the composite joints were studied.

Systematic evaluation of cyanate ester/ epoxidized cresol novolac copolymer resin system for high temperature power electronic packaging applications

The power electronics industry has been actively seeking high temperature stable epoxy molding compound (EMC) materials that can meet the requirements for encapsulating future SiC chips operating at a temperature (250 °C) that exceeds the capability of current epoxy chemistry. This work provides a detailed evaluation of a high heat resistant cyanate ester (CE)/epoxidized cresol novolac (ECN) copolymer system with varied compositions regarding their high temperature performances. Owing to the novolac nature of ECN which provides a high crosslink density, it is found that the copolymers with a low CE concentration (25–33 mol%) are able to produce a comparable glass transition temperature (>230 °C) and decomposition temperature (T10%>400 °C) to those of the high CE formulations. Moreover, long-term high temperature (250 °C) storage test of reveals a less severe weight loss and blistering in the lower CE formulations. A distinguished degradation mechanism involving hydrolysis of unreacted cyanate groups in the high CE compositions was determined through various thermal and chemical analyses. It was concluded that the CE/ECN copolymers with low CE concentrations are promising candidates for the high temperature EMC formulation.

Fast formation of Cu-Sn intermetallic joints using pre-annealed Sn/Cu/Sn composite preform for high-temperature bonding applications

This paper presents the interfacial reaction and growth rate of Cu-Sn intermetallic compounds (IMCs) for various aging times in a composite preform for a die-attach material at high temperature. The feasibility of the composite preform we fabricated for power electronic applications to reduce the long bonding time of transient liquid phase (TLP) bonding was evaluated in this work. After the plating process, the composite preform was composed of Sn layers at both sides of the Cu core layer and the Cu layer. In terms of the aging treatment, the IMC layer was formed rapidly at the Cu-Sn interface in the composite preform by consuming the Sn layers, and the reduction and growth rates of Cu and Cu3Sn were calculated, respectively. We performed the TLP bonding process at 270 °C using various aged composite preforms. The Cu-Sn IMC was formed rapidly on both sides adjacent to the Cu core layer. The thickness of Cu decreased as the aging time elapsed. Therefore, the amount of Cu3Sn adjacent to the Cu core layer increased and the amount of Cu6Sn5 rapidly increased, simultaneously. We investigated the thicknesses and variations of the phase of the joint in the composite preform during the aging treatment process and sequential TLP bonding process for various times. We fabricated pre-annealed Sn/Cu/Sn preforms and performed fast Cu-Sn TLP bonding for high temperature power electronic applications.

Nickel–tin transient liquid phase sintering with high bonding strength for high-temperature power applications

We performed 30Ni–70Sn (wt%) transient liquid phase sintering (TLPS) bonding with micro-sized Ni and Sn powders for high-temperature power applications. A Ni–Sn paste was fabricated and TLPS bonding was performed. We investigated the interfacial reactions, transformations into Ni3Sn4 intermetallic compound (IMC) phases, and joint strength in this study. The Ni–Sn TLPS bonding was an easy and simple process under a relatively low bonding temperature and short bonding time. After TLPS bonding, low melting point Sn element was completely consumed, and the bonded joint was composed of Ni3Sn4 IMCs and the remaining Ni particles. The Ni3Sn4 IMC joint formed with remaining Ni particles was very stable. All the Ni–Sn TLPS samples had high shear strengths of over 70 MPa, and the shear strength was approximately 32% higher than that of the conventional Sn–3.0Ag–0.5Cu solder joint. The Ni–Sn TLPS bonded joints in the present study were not brittle and exhibited superior adhesion strength. This suggests high applicability of the Ni–Sn TLPS bonding for high-temperature power electronic applications in future EV/HEV systems.

Stackable SiC-Embedded Ceramic Packages for High-Voltage and High-Temperature Power Electronic Applications

Abstract This study encompasses the development of a high-voltage and high-temperature–capable package for power electronic applications based on the embedding of silicon carbide (SiC) semiconductor devices in the ceramic circuit carrier such as the direct bonded copper (DBC) substrate. By sealing semiconductor devices into DBC substrates, high temperature, high voltage, and high current capability as well as high corrosion resistance can be achieved compared with the state-of-the-art printed circuit board (PCB) embedding technology. The power devices are attached with high-temperature stable solder and sinter material and are surrounded by thermal conductive ceramic and high-temperature–capable potting materials that enable the complete package to operate at 250°C or above. Furthermore, the single embedded packages can be stacked together to multilevel DBC topologies with increased voltage blocking characteristics. Thus, current limits of the PCB and low-temperature cofired ceramic–based multilayer solutions are exceeded and will be confirmed in the course of this study. This package is designed to carry out the maximal performance of SiC and future wide bandgap devices. It is a promising solution not only for applications in harsh ambient environments such as aerospace and turbine, geothermal well logging, and downhole oil and gas wells but also for hybrid electric/electric vehicle and energy conversion.

Microstructure evolution and growth behavior of Cu/SAC105/Cu joints soldered by thermo-compression bonding

Purpose This paper used a novel technique, which is thermo-compression bonding, and Sn-1.0Ag-0.5Cu solder to form a full intermetallic compound (IMC) Cu3Sn joints (Cu/Cu3Sn/Cu joints). The purpose of the study is to form high-melting-point IMC joints for high-temperature power electronics applications. The study also investigated the effect of temperature gradient on the microstructure evolution and the growth behavior of IMCs. Design/methodology/approach In this paper, the thermo-compression bonding technique was used to form full Cu3Sn joints. Findings Experimental results indicated that full Cu/Cu3Sn/Cu solder joints with the thickness of about 5-6 µm are formed in a short time of 9.9 s and under a low pressure of 0.016 MPa at 450°C by thermo-compression bonding technique. During the bonding process, Cu6Sn5 grew with common scallop-like shape at Cu/SAC105 interfaces, which was followed by the growth of Cu3Sn with planar-like shape between Cu/Cu6Sn5 interfaces. Meanwhile, the morphology of Cu3Sn transformed from a planar-like shape to wave-like shape until full IMCs solder joints were eventually formed during thermo-compression bonding process. Asymmetrical growth behavior of the interfacial IMCs was also clearly observed at both ends of the Cu/SAC105 (Sn-1.0Ag-0.5Cu)/Cu solder joints. Detailed reasons for the asymmetrical growth behavior of the interfacial IMCs during thermo-compression bonding process are given. The compound of Ag element causes a reduction in Cu dissolution rate from the IMC into the solder solution at the hot end, inhibiting the growth of IMCs at the cold end. Originality/value This study used the thermo-compression bonding technique and Sn-1.0Ag-0.5Cu to form full Cu3Sn joints.

Nano and Micro-Scale Simulations of Si/4H-SiC and Si/3C-SiC NN-Heterojunction Diodes

In the last decades, silicon carbide (SiC) based heterostructures have gained a remarkable place in research field due to their exceptional properties. These properties make SiC highly suitable for high temperature, high frequency, and high power electronics applications. The most prominent polytypes (among 200 types) of SiC like 3C-SiC, 4H-SiC and 6H-SiC, have distinctive electrical and physical attributes that make them promising candidates for high performance optoelectronic applications. Silicon (Si) also has been accepted as a promising material for wide range of electronic, optical and optoelectronic applications. Heterostructures fabricated by the direct bonding of SiC polytype and Si may have interesting physical and electrical attributes. In this paper, micro and nano-scale simulations of the nn-heterostructures of Si/4H-SiC and Si/3C-SiC have been done with Silvaco TCAD and QuantumWise Atomistix Toolkit (ATK) softwares respectively. Voltage-current density characteristics of the nanoscale and microscale simulated devices are computed and discussed. In nanoscale devices, the effects of defects due to lattice misplacements (axial displacement of bonded wafers) are also studied. These simulations are the preparation for our future experiments, which are targeted to produce either a high electron mobility diode or a light emitting diode, by direct bonding (diffusion welding) of SiC polytypes.

Stackable SiC Embedded Ceramic Packages for High Voltage and High Temperature Power Electronics Applications

Abstract This paper encompasses the development of a high voltage and high temperature capable package for power electronic applications based on the embedding of SiC (silicon carbide) semiconductor devices in ceramic circuit carrier such as direct bonded copper (DBC) substrate. By sealing the semiconductor devices into DBC substrates, high temperature, high voltage and high current capability as well as high corrosion resistance can be achieved compared to state-of-the-art PCB (printed circuit board) embedding technology. The power devices are attached with high temperature stable solder and sinter material, and are surrounded by thermal conductive ceramic and high temperature capable potting materials that enable the complete package to operate at 250 °C or above. Furthermore, the single embedded packages can be stacked together to multilevel DBC topologies with increased voltage blocking characteristics. Thus, current limits of PCB and LTCC (low-temperature co-fired ceramic) based multilayer solutions are exceeded and will be confirmed in the course of this study. This package is designed to carry out the maximal performance of SiC and future WBG (wide band-gap) devices. It is a promising solution for applications in harsh ambient environment such as aerospace and turbine, geothermal well logging, down hole-well oil & gas, but also applicable for HEV/EV (hybrid electric/electric vehicle) and energy conversion.

Development of a Simplistic Method to Simulate the Formation of Intermetallic Compounds in Diffusion Soldering Process

A simplistic simulation technique has been developed for computing the individual intermetallic compound (IMC) thickness which is formed in substrate-solder (Cu-Sn) systems during the diffusion soldering process in high-temperature power electronic applications. The method requires the time-dependent temperature profile for the soldering process and the growth rate parameters (e.g. concentration gradient, diffusion coefficient, activation energy, etc.) for the development of IMC layers as input. The method is suitable for predicting the thickness of an intermetallic phase layer during the diffusion soldering process. As such, it can be used in high-temperature power electronic application’s solder processing to enhance the reliability and lifetime of solder interconnections by allowing the control of the thickness of IMC layers. The method is demonstrated for IMC growth between pure copper as substrate and pure Sn as solder material. The growth behavior of the IMC layer is increased with increasing temperature over time according to the Arrhenius theory in the temperature range between 24°C to 260°C. To simulate the formation of IMC thickness in diffusion soldering interconnections, a simplistic way has been attempted using the popular commercial finite element simulation tool Comsol Multiphysics and scientific computing application ‘Matlab’. By means of transient thermal input, the diffusion-controlled intermetallic phase formation is simulated here. Few assumptions are taken care of this simulation process, for example, no convection, no reaction, solid-solid diffusion, no the pressure effect on the computational domain.

Simulation study of a 4H-SiC lateral BJT for monolithic power integration * * Project supported by the National Natural Science Foundation of China (No. 51577054).

Power integration based on 4H-SiC is a very promising technology for high-frequency and high-temperature power electronics applications. However, the fabrication processes used in Si BiCMOS technology is not applicable in 4H-SiC at present, and few studies on the monolithic power integration of the SiC signal devices and power devices have been reported. In this paper, we propose a novel lateral BJT structure, which is suitable for monolithically integrating with the vertical power BJT on the same epitaxial wafer at the cost of one additional mask. The signal BJT’s static and dynamic characteristics are comprehensively investigated by TCAD simulation. Simulation results show that the common-emitter current gains of the 4H-SiC signal BJT are 133 and 52 at room temperature and 300 °C, respectively. Its implementation in an inverter shows that its switching time is about 200 ns.

Initial interfacial reactions of Ag/In/Ag and Au/In/Au joints during transient liquid phase bonding

A comparative study of initial interfacial reactions and kinetics of AgIn and AuIn as die-attach materials for high-temperature power electronics applications was performed in this study. Sequential interfacial reactions and transformations of the In solder to intermetallic compound (IMC) phases of the Ag/In/Ag and Au/In/Au joints were investigated and compared for transient liquid phase (TLP) bonding at 190 °C for 1 min under different bonding pressures. The interfacial reaction of the Ag/In/Ag joint was faster than that of the Au/In/Au joint under same bonding conditions. In the Ag/In/Ag joints, the TLP joint was fully converted into the Ag-rich Ag2In IMC. On the other hand, the Au/In/Au TLP joint was composed of three AuIn IMCs of Au7In3, AuIn, and AuIn2.

A low temperature die attach technique for high temperature applications based on indium infiltrating micro-porous Ag sheet

A low-temperature die attach method based on In infiltrating micro-porous Ag sheet was proposed for high temperature power electronic applications. The bonding temperature was decreased down to 180 °C, reducing the thermal stress caused by coefficient of thermal expansion (CTE) mismatch between die and direct bonded copper (DBC). In the bonding process, the effect of In infiltrated the micro-porous Ag sheet was driven by capillary force. The high specific area of micro-porous Ag sheet accelerated the consumption of the low-melting-point In phase. The compositions evolution of the bondline was investigated. When reflowed at 200 °C for 10 min, the melting point of the bondline was increased to 660 °C due to the formation of Ag9In4. Moreover, after aging at 300 °C for 72 h, the melting point of the bondline was further increased to more than 695 °C, due to the formation of (Ag). Furthermore, shear tests at both room temperature (RT) and elevated temperatures were conducted. The shear strength of the samples reflowed at 200 °C for 10 min reached 40.2 MPa at RT. After aging at 300 °C for 168 h, the shear strengths reached 37.9, 26.2, 13.0 MPa at 300, 400, 500 °C, respectively. In addition, ductile features were observed in the fracture morphology of the aged samples. Vickers hardness dramatically dropped after initial aging and slowly decreased thereafter. The performance of the whole bondline turns to be more like a metal rather than intermetallic compounds (IMCs) with the aging process going on.

The mechanism of pore segregation in the sintered nano Ag for high temperature power electronics applications

It is widely accepted that nano pores of sintered nanoparticles can coalesce into micro pores during high temperature service. When applying sintered nanoparticles in power electronics, the pore segregation and delamination seriously degrade the bond strength and thermal conductivity, but the reason is still not well understood. In this paper, both finite element analysis and experimental results confirmed that thermal stress is the main driving force for this phenomenon, which was not considered in the previous study. The effect of pore segregation on performance and reliability of power devices is also discussed.

Simulations of Heterostructures Based on 3C-4H and 6H-4H Silicon Carbide Polytypes

In the last decade, silicon carbide (SiC) has gained a remarkable position among wide bandgap semiconductors due to its high temperature, high frequency, and high power electronics applications. SiC heterostructures, based on the most prominent polytypes like 3C-SiC, 4H-SiC and 6H-SiC, exhibit distinctive electrical and physical properties that make them promising candidates for high performance optoelectronic applications. The results of simulations of nn-junction 3C-4H/SiC and 6H-4H/SiC heterostructures, at the nanoscale and microscale, are presented in this paper. Nanoscale devices are simulated with QuantumWise Atomistix Toolkit (ATK) software, and microscale devices are simulated with Silvaco TCAD software. Current-voltage (IV) characteristics of nanoscale and microscale simulated devices are compared and discussed. The effects of non-ideal bonding at the heterojunction interface due to lattice misplacements (axial displacement of bonded wafers) are studied using the ATK simulator. These simulations lay the groundwork for the experiments, which are targeted to produce either a photovoltaic device or a light-emitting diode (working in the ultraviolet or terahertz spectra), by direct bonding of SiC polytypes.

Cu-Sn Intermetallic Compound Joints for High-Temperature Power Electronics Applications

Cu-Sn solid–liquid interdiffusion (SLID) bonded joints were fabricated using a Sn-Cu solder paste and Cu for high-temperature power electronics applications. The interfacial reaction behaviors and the mechanical properties of Cu6Sn5 and Cu3Sn SLID-bonded joints were compared. The intermetallic compounds formed at the interfaces in the Cu-Sn SLID-bonded joints significantly affected the die shear strength of the joint. In terms of thermal and mechanical properties, the Cu3Sn SLID-bonded joint was superior to the conventional solder and the Cu6Sn5 SLID-bonded joints.