High Step Coverage Research Articles

Super-conformal TiN thin film deposition by carrier pulse purge atomic layer deposition system: Chamber design optimization with computational fluid dynamics

Owing to the increase in demand for the shrinkage of semiconductor design rules and the advent of the three-dimensional structure of semiconductor devices, atomic layer deposition (ALD) has emerged as an attractive alternative to conventional chemical vapor deposition techniques. Although the development of precursors and characterization of ALD films have been widely studied, few studies have been conducted on the modification of ALD parameters and optimization of the ALD process. In this study, an advanced ALD titanium nitride (TiN) system was designed using a pumping and purging simulationBased on the simulation results, we adopted a carrier pulse purge method, where TiCl4 fed, purge N2, pulse purge N2, purge N2, NH3 fed, purge N2, pulse purge N2, and purge N2 were alternatively injected into the chamber in the ALD cycle. Compared to the conventional purge method, the carrier pulse purge method can reduce the ALD cycle time by 18.27% and yields a high-quality (high step coverage, 98 %) TiN film with lower electrical resistivity and chlorine impurity. This carrier pulse purge method can ultimately lead to improved throughput and productivity in the semiconductor industry by reducing the ALD cycle time.

Electrochemical Grafting of an Aminated Poly(methyl methacrylate) (PMMA)-like Liner onto a Silicon Surface for the Metallization of Microfeatures

The micro/nanofabrication industry’s transition from physically deposited dielectric films toward relatively inexpensive insulating polymeric materials faces a challenging metallization step in progression. In this work, we demonstrate a metallization scheme constituting simple and completely aqueous chemical steps─from Si passivation to metallization. We first propose a versatile diazonium-based electrochemical process to graft an in situ aminated poly(methyl methacrylate) (PMMA) liner onto Si microfeatures with high step-coverage. These amine-terminated groups functionalize the grafted PMMA-like liner with palladium chloride complex activators and allow direct autocatalytic deposition of Ni–B film while avoiding any further amination step as conventionally required for polymeric surfaces. The obtained Ni–B film exhibiting high uniformity, strong adhesion to the polymer film, and excellent step-coverage from the top, sidewall, and bottom of the microstructures fulfills all requirements of a conducting seed layer for the subsequent electrolytic deposition of copper.

Performance Comparison between Atomic-layer-deposited Al2O3/HfO2 Nanolaminate and Parylene C for Implantable Devices with High Step Coverage Using Accelerated Life Testing

Performance Comparison between Atomic-layer-deposited Al2O3/HfO2 Nanolaminate and Parylene C for Implantable Devices with High Step Coverage Using Accelerated Life Testing

Advanced barrier and seed layer deposition enabling multiple type of TSVs integration

TSV integration is a key technology allowing heterogeneous devices 3D integration. However, depending on the targeted application, various TSV sizes and integration schemes exist, all requesting very high aspect ratio. The most common integration is the Mid-process TSV for which aspect ratio is required to be higher than 10:1 whatever application. In the case of large interposers, silicon thickness has to be increased to limit the deformation of the substrate due to highly stressed devices. Same requirements are made by photonic interposers which use thick SOI substrate leading to high warpage during integration. In the opposite, imagers requires to save silicon surface thus reduce TSV size and keep out zone. Silicon thickness has to be kept in the 100 μm range leading then the aspect ratio of the TSV to increase. Recently, Hybrid bonding progresses allowed a new type of TSV to be introduced : High Density TSVs for imagers. In this application, micrometer range TSV have to be filled with a Silicon thickness reduction limited to 10 μm by grinding process control. In order to allow the metal filling of all those type of structures, we have developed a highly conformal barrier and seed layer processes using standard materials for easier integration. The process is based on the use of MOCVD TiN as a barrier. This material is deposited using TDMAT precursor which allows low temperature deposition (200 °C)[1] which extends also the polyvalence of the process toward polymer bonded integrations. The very high step coverage of this process, reported at more than 30% in 20:1 aspect ratio coupled to high resistance to copper diffusion allows as thin as 20 nm barrier thickness which appears relevant economically (for deposition and CMP) and for stress consideration, compared to the well known but thicker PVD TaN process. Considering seed layer, the eG3D process[2] was brought to a high maturity allowing it to be integrated in an applied material raider tool coupled to TSV filling reactors. This process, based on electrografting of copper has already proved a step coverage of more than 50% in 12:1 aspect ratio structures. The presented work shows that the same process requires only deposition parameters change to be able to fully cover 10×150 μm Mid-process TSV as well as 1×10 μm High density ones. The excellent step coverage of this process allowed as thin as 200 nm (for 10×120 μm TSVs) and 100 nm (for (1×10 μm ones) deposited thicknesses to ensure perfect coverage of the structures. eG3D process also has the ability to be used as a repair process for non-continuous widely used PVD Cu seed layers but also be deposited directly on the barrier material. These 2 layers were evaluated together in a 300mm TSV integration schemes of both 10×120 mid process and 1×10 μm High Density structures and qualified electrically. The paper will discuss the deposition process development leading to simultaneously allow copper filling of the very wide range of TSVs on the same process equipment and using the same chemicals. We will then present integration results as well as electrical test of TSV daisy chains of both mid and High density TSVs showing excellent yield for all TSV size and integration schemes.

Electroless Grafting of Polymer Insulation Layers in Through-Silicon Vias

A through-silicon via (TSV) with a polymeric insulation layer is promising in three-dimensional packaging technology because of its outstanding electrical properties. In this study, we present an electroless grafting method to realize the fabrication of a thin insulation layer in high aspect ratio TSVs. The proposed method is based on the polymerization of a vinyl monomer and an aryl diazonium salt on a silicon surface. Both poly(acrylic acid) and poly(methyl methacrylate) insulation layers were successfully prepared in TSVs to demonstrate the feasibility of the proposed method to fabricate hydrophilic and hydrophobic layers. The resulting polymer insulation layer exhibited high step coverage and superior dielectric properties. The electroless grafting method is a novel synthesis route to prepare polymeric insulation layers with outstanding dielectric properties in high aspect ratio TSVs.

Effect of thickness on the properties of ZnO thin films prepared by reactive RF sputtering

This work reports structural and electrical properties of ZnO thin film deposited by reactive RF sputtering at the room temperature, for thin film transistor (TFT) applications. To study the thickness dependent effect, ZnO thin film of thicknesses 100, 200 and 800 nm were deposited over p-type silicon substrate. Structural properties of thin films have been characterized using X-ray Diffraction (XRD) and Atomic Force Microscopy (AFM). XRD analysis of 100 and 200 nm thick films shows dominant cubic phase of ZnO along with small presence of ZnO2, while; XRD analysis of 800 nm thick film confirms strong c-axis growth of wurtzite (W) ZnO. The XRD result confirm the polycrystalline nature of the thin film and shows that crystallinity improves with the film thickness. The AFM results confirm high step coverage of deposited thin films. From the thermionic transport model across the grain boundary it was observed that with an increase in film thickness mobility of carriers increases. The sheet resistance of undoped 100 and 200 nm ZnO film is found to be approximately 7 × 1011 Ω/□; while, the sheet resistance of 800 nm thick ZnO film shows almost 10 time reduction to 6.025 × 1010 Ω/□, owing to its improved crystallinity.

Using the light scattering properties of multi-textured AZO films on inverted hemisphere textured glass surface morphologies to improve the efficiency of silicon thin film solar cells

We report the light scattering characteristics of multi-textured aluminum-doped zinc oxide (AZO) thin films with high optical transmittance, haze ratio and step coverage for amorphous silicon thin film solar cells (a-Si TFSCs). Multi-textured AZO films were deposited on inverted hemisphere textured (IHT) glass surface morphologies. Multi-textured process was used to create modulated surface morphologies with micro and nano-features useful for the light scattering in visible as well as near-infrared wavelength region. Highly transparent IHT glass surface morphologies with high haze ratio were prepared by wet chemical etching of periodic glass substrates. Total transmittance of the IHT glass substrates showed higher average values (91.38–93.40%) as compared to that of bare glass (90.94%) in the visible wavelength region due to lower reflectance. Multi-textured AZO films showed higher rms roughness 100.479 nm, optical transmittance 82.60% and haze ratio 75.09% in the visible wavelength region. X-ray photoelectron spectroscopic analysis of multi-textured AZO thin films was used to study the atomic compositions and chemical binding states. Multi-textured AZO films with high transmittance and haze ratio were used as front transparent conductive oxide layers for the fabrication of a-Si TFSCs using an absorber layer thickness of 400 nm. Multi-textured AZO films deposited on the optimal textured glass surface morphologies yield the maximum performance of a-Si TFSCs as; Voc = 871 mV, Jsc = 16.55 mA/cm2, FF = 66.6% and η = 9.61%. An enhancement of photocurrent was noticed from 15.64 to 16.55 mA/cm2 for the a-Si TFSCs deposited on as deposit AZO to optimal textured AZO films.

Effect of reactor pressure on the conformal coating inside porous substrates by atomic layer deposition

Atomic layer deposition (ALD) is renowned for its step coverage in porous substrates. Several emerging applications require a combination of this high step coverage with high throughput ALD, like spatial ALD. Often, high throughput ALD is performed at atmospheric pressure, and therefore, the effect of reactor pressure on the saturation dose is investigated. ALD inside porous substrates is governed by three key parameters: the reaction probability, the pore aspect ratio, and the precursor diffusion coefficient, of which the latter one contains the reactor pressure dependency. The effect of these parameters on the saturation dose is validated using Monte Carlo modeling, where the reactor pressure dependency is included through the mean free path. A reaction-limited and a diffusion-limited regime can be identified, and it is shown that for many realistic experimental conditions, even at low reactor pressures, the saturation dose is in the diffusion-limited regime. An expression for the pressure dependent saturation dose in the diffusion-limited regime is derived. For small pore diameters, the saturation dose is pressure independent, but for larger pores, higher saturation doses are required for atmospheric reactor pressures than for low reactor pressures. However, as high reactor pressures enable much higher precursor partial pressures than low reactor pressures, the resulting saturation times can be much shorter at atmospheric pressure than low pressure. Often, high surface area porous substrates will lead to supply limited conditions, and increased saturation times have to be taken into account. These results show that the atmospheric pressure ALD can be used for high throughput ALD inside porous substrates, as long as high precursor partial pressures and molar flows can be applied. This is experimentally demonstrated by a near 100% step coverage obtained by atmospheric spatial ALD of alumina in high aspect ratio pores.

Dual ICP Si Etching and Vapor Deposition Polymerization Liner for Backside Via-Last TSV Packaging Process Integration

Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. To realize above-mentioned Smart Technologies, high-density, low-power consumption, wide-bandwidth, fast-operation semiconductor devices as well as smart functional devices enabled by integrating functionalities with advanced semiconductor technologies including CMOS technologies are necessary. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and 2.1D PCB packaging are among key technologies to satisfy the requirements from the both smart semiconductor devices and smart functional devices. "Hetero 3D stacked" technologies are gathering the most attention from now on. These technologies can make a high density packaging interconnection by using TSV on the each function devises. Heterogynous 3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the cost of TSV fabrication is not still solved. In particular, the management of barrier metal film deposition on the smooth surface is most important technology for Cu diffuse protection [1]. On the other hand, TSV isolation liner materials with high step coverage and lower temperature deposition on the smooth surface for high frequency devices will be necessary in the future. “Scallop-free” etching process has developed for TSV fabrication [2]. In this paper, our high-density packaging technologies including scallop-free, low-temperature processed TSV solution for via-last packaging scheme and 2.1D packaging solutions on large panel build-up board by semiconductor manufacturer tools will be introduced. Especially, backside Via-last TSV process integration was proposed by “A Novel Dual ICP Plasma” Si etching and low-temperature "Vapor Deposition Polymerization (VDP)" liner (< 200 degree ) for lower-cost and low-stress hetero 3D chip stacked. “A Novel Dual ICP Plasma” is using 2 RF modes mixed ICP plasma. One is high frequency RF mode. And, another is low frequency RF mode. This plasma is able to generate high-density plasma (High etch rate), and also “Scallop-free” smooth etching. This is a kind of “Non-Bosch” process. On the other hand, this dual ICP plasma can carry out “Bosch” process at the same module. This system is very unique etching tool that can use for distinguishing between "Bosch" and "non-Bosch" to TSV cost reduction.

TiCl4 Barrier Process Engineering in Semiconductor Manufacturing

Titanium nitride (TiN) not only was utilized in the wear-resistant coatings industry but it was also adopted in barrier processes for semiconductor manufacturing. Barrier processes include the titanium (Ti) and TiN processes, which are commonly used as diffusion barriers in via/contact applications. However, engineers frequently struggle at the via/contact module in the beginning of every technology node. As devices shrink, barrier processes become more challenging to overcome the both the physical fill-in and electrical performance requirements of advanced small via/contact plugs. The aim of this paper is to investigate various chemical vapor deposition (CVD) TiCl4-based barrier processes to serve the application of advanced small via/contact plugs and the metal gate processes. The results demonstrate that the plasma-enhanced chemical vapor deposition (PECVD) TiCl4-based Ti process needs to select a feasible process temperature to avoid Si surface corrosion by high-temperature chloride flow. Conventional high step coverage (HSC) CVD TiCl4-based TiN processes give much better impurity performance than metal organic chemical vapor deposition (MOCVD) TiN. However, the higher chloride content in HSC film may degrade the long-term reliability of the device. Furthermore, it is evidenced that a sequential flow deposition (SFD) CVD TiCl4-based process with multiple cycles can give much less chloride content, resulting in faster erase speeds and lower erase levels than that of conventional HSC TiN.

Study on TSV isolation liners for a Via Last approach with the use in 3D-WLP for MEMS

This paper discusses approaches for the isolation of deep high aspect ratio through silicon vias (TSV) with respect to a Via Last approach for micro-electro-mechanical systems (MEMS). Selected TSV samples have depths in the range of 170ź270 µm and a diameter of 50 µm. The investigations comprise the deposition of different layer stacks by means of subatmospheric and plasma enhanced chemical vapour deposition (PECVD) of tetraethyl orthosilicate; Si(OC2H5)4 (TEOS). Moreover, an etch-back approach and the selective deposition on SiN were also included in the investigations. With respect to the Via Last approach, the contact opening at the TSV bottom by means of a specific spacer-etching method have been addressed within this paper. Step coverage values of up to 74 % were achieved for the best of those approaches. As an alternative to the SiO2-isolation liners a polymer coating based on the CVD of Parylene F was investigated, which yields even higher step coverage in the range of 80 % at the lower TSV sidewall for a surface film thickness of about 1000 nm. Leakage current measurements were performed and values below 0.1 nA/cm2 at 10 kV/cm were determined for the ParyleneF films which represents a promising result for the aspired application to Via Last MEMS-TSV.

Low-temperature SiON films deposited by plasma-enhanced atomic layer deposition method using activated silicon precursor

It has not been an easy task to deposit SiN at low temperature by conventional plasma-enhanced atomic layer deposition (PE-ALD) since Si organic precursors generally have high activation energy for adsorption of the Si atoms on the Si-N networks. In this work, in order to achieve successful deposition of SiN film at low temperature, the plasma processing steps in the PE-ALD have been modified for easier activation of Si precursors. In this modification, the efficiency of chemisorption of Si precursor has been improved by additional plasma steps after purging of the Si precursor. As the result, the SiN films prepared by the modified PE-ALD processes demonstrated higher purity of Si and N atoms with unwanted impurities such as C and O having below 10 at. % and Si-rich films could be formed consequently. Also, a very high step coverage ratio of 97% was obtained. Furthermore, the process-optimized SiN film showed a permissible charge-trapping capability with a wide memory window of 3.1 V when a capacitor structure was fabricated and measured with an insertion of the SiN film as the charge-trap layer. The modified PE-ALD process using the activated Si precursor would be one of the most practical and promising solutions for SiN deposition with lower thermal budget and higher cost-effectiveness.

Silicon interposer process development for advanced system integration

3D integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. Through silicon via (TSV) is one of the key elements for 3D integration. This paper presents different liner and barrier/seed approaches for realizing 10×100μm void-free copper filled TSVs. It is found that the plasma enhanced chemical vapor deposition (PECVD) TEOS film shows high dielectric constant, high leakage current and low step coverage. The thermal oxide film offers near 100% step coverage and low leakage current, but the growth rate is very slow. Hence a thermal oxide/PECVD TEOS bi-layer is formed to combine the advantage of each layer. Apart from the conventional plasma vapor deposition (PVD) barrier/seed, a novel metallization scheme with an atomic layer deposition (ALD) barrier and electroless deposited (ELD) seed is also investigated, which shows big potential for further scaling up the aspect ratio of TSV. Finally, a silicon interposer with thousands of TSVs is fabricated and 2.5D integration of device chips is demonstrated, from which good eye diagram is observed.

Research on Setting Adjustment of Line Protection

In order to avoid incorrect setting from being a hidden fault source which threats the stable operation of power system, setting adjustment algorithm of line protection is proposed. Through setting detection and setting rectification the algorithm amends incorrect setting and reduces the number of mismatch protection to the greatest extent. A method of calculating high step coverage of interphase current protection based on node impedance matrix is also proposed in this paper. The example shows the proposed algorithm is practical.

SU-8 based microprobes with integrated planar electrodes for enhanced neural depth recording

Here, we describe new fabrication methods aimed to integrate planar tetrode-like electrodes into a polymer SU-8 based microprobe for neuronal recording applications. New concepts on the fabrication sequences are introduced in order to eliminate the typical electrode–tissue gap associated to the passivation layer. Optimization of the photolithography technique and high step coverage of the sputtering process have been critical steps in this new fabrication process. Impedance characterization confirmed the viability of the electrodes for reliable neuronal recordings with values comparable to commercial probes. Furthermore, a homogeneous sensing behavior was obtained in all the electrodes of each probe. Finally, in vivo action potential and local field potential recordings were successfully obtained from the rat dorsal hippocampus. Peak-to-peak amplitude of action potentials ranged from noise level to up to 400–500μV. Moreover, action potentials of different amplitudes and shapes were recorded from all the four recording sites, suggesting improved capability of the tetrode to distinguish from different neuronal sources.

Kinetics of Stop-Flow Atomic Layer Deposition for High Aspect Ratio Template Filling through Photonic Band Gap Measurements

Atomic layer deposition (ALD) is shown as a unique method to produce high aspect ratio (AR) nanostructures through conformal filling and replication of high AR templates. The stop-flow process is often used as an alternative to the conventional continuous flow process to obtain high step coverage. However, there is a need for understanding the deposition kinetics and optimizing the deposition process to fabricate defect-free nanostructures. In this Article, TiO2 ALD in high AR self-assembled opal photonic crystal templates was performed in stop-flow fill−hold−purge process in comparison with continuous flow pulse−purge process. Photonic band gap properties of opal templates were characterized and compared with simulated band diagrams for quantitative investigation of filling kinetics and the effect of shrinking pore size on filling uniformity. Γ−L bands in the transmittance spectra of ALD-infiltrated opals accurately represented the depth profile of the depositions without the need for expensive sample preparation techniques and characterization tools. It was found that the stop-flow process attains higher Knudsen flow rates of precursor gases, thereby achieving homogeneous and complete filling at considerably lower cycle time.

Enabling Robust Copper Fill of High Aspect Ratio Through Silicon Vias

Today's Through Silicon Via (TSV) processes are limited to aspect ratios of 10:1. High performance logic devices drive the need for aspect ratios approaching 20:1 in order to achieve the desired performance while simultaneously reducing costs. The reduced via area required on the wafer enables the designer to utilize less real estate on the die to reduce cost or to potentially add redundant vias to improve yield. However, current conventional processes and techniques are not capable of achieving robust fill on aspect ratios greater than 12:1. This presentation will highlight the technical challenges in achieving robust copper fill on super high aspect ratio TSV structures. Additionally, a compelling, economic solution pathway will be presented that integrates a low temperature conformal high quality dielectric isolation layer, a high step coverage Cu barrier / seed technology and a void free high speed electroplating process with a wide process window that could accelerate the adoption of the high aspect ratio TSV design schemes.

Thin Polymer Films with High Step Coverage in Microtrenches by Initiated CVD

AbstractInitiated (i)CVD is used to deposit thin films of poly(cyclohexylmethacrylate) (pCHMA) in microtrenches of depth 7 µm and widths 1‐5 µm. By changing the fractional saturation of the monomer vapor, step coverage of 0.85 is achieved for the highest aspect ratio trench studied while maintaining a deposition rate of 15 nm min−1. An analytical model for determining the sticking probability of the initiating radical (CH3)3CO· is developed, and is experimentally shown to be a function of the fractional saturation of the monomer vapor. For the conditions studied, the sticking probability is in the range 1.1 × 10−2–5.0 × 10−2. These results suggest that iCVD proceeds via the reaction of a vapor‐phase initiating radical with a surface‐adsorbed monomer.

High-Speed Rotating-Disk Chemical Vapor Deposition Process for In-Situ Arsenic-Doped Polycrystalline Silicon Films

We have developed high-speed rotating-disk chemical vapor deposition (CVD) equipment for polycrystalline silicon (poly-Si) films. This CVD equipment has an enhanced ability to reduce the boundary layer thickness at a given temperature above a wafer surface, and to suppress vapor-phase reactions. We investigated in-situ arsenic-doped poly-Si film deposition using silane (SiH4), arsine (AsH3) and nitrogen (N2) in a high-speed rotating-disk CVD as functions of AsH3 flow rate and deposition temperature. Both the deposition rate and resistivity decreased with increasing AsH3 flow rate. A deposition rate of 120 nm/min, a resistivity of 16 mΩ·cm, a film thickness nonuniformity of ±5%, and a number of particles of less than 20 (over 200 nm in diameter) were achieved at a deposition temperature of 680°C for in-situ arsenic-doped poly-Si deposition on a 200-mm-diameter silicon (Si) wafer. Moreover, it was confirmed that the concentration of As in the poly-Si film was low at the initial stage of deposition, and that this process has a high gap filling capability in a hole of 0.18 µm width and 7 µm depth. It was also confirmed that there were conditions for a high step coverage of more than 1. These properties are inferred to be due to the adsorbed AsH3 preventing the adsorption of SiH4.

TN 모드와 FFS 모드에서 Pretilt Angle이 전기 광학 특성 및 동력학 안정성에 미치는 영향에 관한 연구

We studied on the electro-optic characteristics and dynamic stability according to an undesirably defined pretilt angle induced in high step coverage of pixel area for the Twisted Nematic (TN) / Fringe-Field Switching (FFS) mode. In case of the TN mode, LC directors twist reversely near the edges of thin-film-transistor and black matrix where the pretilt angle of the LC is not well defined. Therefore, the voltage-dependent dynamics of the LC in TN mode is unstable and shows the bad electro-optic characteristics. On the other hand, in case of the FFS mode, the LCs are twisted parallel to the bottom substrate by fringe electric field and the electro-optic characteristic is not influenced by the pretilt angle of the LC which is not well defined.