High-speed Signal Transmission Research Articles

Research on high-speed digital optical signal jitter measurement technology based on clock recovery algorithm using eye diagram opening area

With the rapid development of information technology, high-speed digital optical signal transmission technology has become the core of modern communication networks. However, the increase in transmission rates brings challenges such as noise, distortion, and interference, which affect the accuracy of clock recovery. To address these issues, this study proposes a clock recovery algorithm based on the eye diagram opening area to improve the accuracy and efficiency of high-speed digital optical signal jitter measurement. The proposed method extracts clock information from the signal using the opening area and curvature characteristics of the eye diagram for jitter measurement. Experimental results demonstrate that the clock recovery algorithm based on the eye diagram opening area can stably reconstruct the signal eye diagram and obtain jitter parameters under different optical power conditions. At optical powers of −7.2 dBm, −12.2 dBm, and −17.2 dBm, the Q-factors were 8.8, 7.6, and 4.3, respectively, and the RMS jitter values were 12.2 ps, 13.4 ps, and 21.2 ps, respectively. At optical powers of −2.3 dBm, 0.1 dBm, 2.4 dBm, 4.6 dBm, and 6.0 dBm, the Q-factors were 9.1, 9.3, 9.5, 9.7, and 10.0, respectively, and the average jitter values were 8.9 ps, 8.5 ps, 8.0 ps, 7.5 ps, and 7.0 ps. These results indicate that the proposed algorithm performs excellently under low optical power conditions and maintains high recovery accuracy even when jitter increases at higher optical powers. The clock recovery algorithm based on the eye diagram opening area significantly improves the accuracy and stability of high-speed digital optical signal jitter measurement, enriches the theoretical research of clock recovery algorithms, and shows significant advantages in improving signal transmission quality, reducing bit error rate, and enhancing communication link reliability. The research outcomes provide key technical support for the optimization of modern high-speed optical communication systems.

Ultrastable 3D Heterogeneous Integration via N-Heterocyclic Carbene Self-Assembled Nanolayers.

The commercialization of 3D heterogeneous integration through hybrid bonding has accelerated, and accordingly, Cu-polymer bonding has gained significant attention as a means of overcoming the limitations of conventional Cu-SiO2 hybrid bonding, offering high compatibility with other fabrication processes. Polymers offer robust bonding strength and a low dielectric constant, enabling high-speed signal transmission with high reliability, but suffer from low thermomechanical stability. Thermomechanical stability of polymers was not achieved previously because of thermal degradation and unstable anchoring. To overcome these limitations, wafer-scale Cu-polymer bonding via N-heterocyclic carbene (NHC) nanolayers was presented for 3D heterogeneous integration, affording ultrastable packing density, crystallinity, and thermal properties. NHC nanolayers were deposited on copper electrodes via electrochemical deposition, and wafer-scale 3D heterogeneous integration was achieved by adhesive bonding at 170 °C for 1 min. Ultrastable conductivity and thermomechanical properties were observed by the spatial mapping of conductivity, work function, and force-distance curves. With regard to the characterization of NHC nanolayers, low-temperature bonding, robust corrosion inhibition, enhanced electrical conductivity, back-end-of-line process compatibility, and fabrication process reduction, NHC Cu/polymer bonding provides versatile advances in 3D heterogeneous integration, indicating that NHC Cu/polymer bonding can be utilized as a platform for future 3D vertical chip architectures.

A 25 Mbps 15 ns Propagation Delay 150 kV/μs CMTI Configurable Dual-Channel Capacitive Digital Isolation Driver.

Electrical isolation devices are essential components for safeguarding the reliability of electronic systems under harsh conditions. Digital isolators are widely used in low-power circuits due to their high immunity to disturbances. In this paper, a capacitive digital isolator for high-efficiency power supply scenarios is proposed with a high common-mode transient immunity (CMTI) and high data transmission rate. The on-off keying (OOK) modulation technique is used to ensure a high speed and accurate signal transmission. A fully integrated high-voltage level-shift driver with an ns-scale delay is proposed for increasing the drive capacity. Post-simulation results in Cadence IC 6.1.7 with the standard 0.18 μm CMOS process show that the proposed architecture achieves a 25 Mbps data transmission rate and 15 ns typical propagation delay with output peak currents of 2 A/4 A, respectively. Meanwhile, a CMTI of more than 150 kV/μs is realized.

Design of Indoor Visible Light Communication PAM4 System

Four-level pulse amplitude modulation (PAM4) can transmit more information in the same symbol interval, effectively improving the information transmission rate and frequency band utilization of visible light communication (VLC). This paper proposes a method for encoding and decoding the PAM4 signal based on FPGA. The PAM4 signal is studied and analyzed under different channel noise models. The research results show that the bit error rate (BER) performance of the PAM4 signal is the best under the additive noise model. The influence of the multiplicative noise on the BER of the PAM4 signal is much greater than that of the additive noise. The BER performance of the PAM4 signal depends on the variance of the noise data. The greater the variance, the worse the BER performance. At the same time, an indoor VLC system based on PAM4 is designed. The simulation results verify that the system scheme is feasible and provides a way to further realize high-speed signal transmission.

Enhancing the dielectric and thermal properties of polytetrafluoroethylene-based composites through designing and constructing a novel interfacial structure

Polytetrafluoroethylene (PTFE) is widely used as a fundamental core material for high-frequency and high-speed signal transmission fields due to its excellent dielectric properties. However, the high coefficient of thermal expansion (CTE) characteristic of PTFE severely limits its practical application. The CTE of PTFE can be reduced by filling with SiO2, which is always accompanied by a rapid deterioration of dielectric properties due to the poor interfacial compatibility between SiO2 and PTFE matrix. In this paper, the challenge of synergistic regulation of dielectric and CTE properties for PTFE-based composites is overcome by constructing an interfacial structure with physical interactions. Micro-mesoporous SiO2 (mSiO2) is prepared and introduced as a filler, compared with smooth surface SiO2 (sSiO2), the presence of micro-mesoporous in mSiO2 allows PTFE molecular chains to be adsorbed on the surface or in the pore channels of mSiO2, which improves the interfacial combination of the mSiO2/PTFE composites through the physical interaction between mSiO2 and PTFE. The results show that mSiO2/PTFE composite exhibits a lower CTE (58 ppm °C−1) while maintaining a lower dielectric constant (εr, 2.29, 30 GHz) with dielectric loss (tan δ, 2.31 × 10−3, 30 GHz) at a filler addition of 30 vol%, as compared with that of the sSiO2/PTFE composites. This work provides a new strategy for fabricating PTFE-based composites with low CTE as well as low εr and tan δ.

Coverage and reliability improvement of copper metallization layer in through hole at BGA area during load board manufacture

Abstract The dimple of ball grid array (BGA) area with 70 mm × 70 mm size on load board for high performance integrated circuit final test is investigated by shadow moire at first, the dimple of BGA area decreases from 184.3 to 97.1 μm when six additional prepregs with 60 mm × 60 mm size are added at BGA area before hot lamination process. The micromorphology and stress/strain simulation are conducted to improve the coverage and reliability of copper metallization layer in through hole at that BGA area. The microcracks of electroless copper layer at the position of glass fiber and inner layer copper pad, which leads to serious crack after solder float, are well covered by subsequent electroplating copper layer. When the through holes at BGA area with 0.2 mm diameter and 7.0 mm depth are fabricated based on insulating dielectric material used for high-speed signal transmission, the simulation results point out that IT968 is better than M6G for the thermal shock reliability of through hole metallization layer. A load board vehicle with 126 layers and 8.3 mm thickness based on IT968 shows good interconnection structure reliability after 12 times 288°C solder float.

Low Loss Hybrid-Plane PCB Structure for Improving Signal Quality in High-Speed Signal Transmission

Low Loss Hybrid-Plane PCB Structure for Improving Signal Quality in High-Speed Signal Transmission

Mechanical model of back-drilling high-speed printed circuit boards with eccentricity effects

The rapid development of fifth-generation (5 G) communication technology is placing greater demands on the performance of high-speed printed circuit boards (PCBs). Back-drilling plays a crucial role in achieving high-frequency and high-speed signal transmission and is a key technology for improving the signal integrity of high-speed PCBs. The thrust force is considered the main factor affecting hole quality when drilling PCBs. Accurately predicting the thrust force is essential for optimizing the back-drilling process. However, back-drilling thrust force is strongly coupled with eccentricity, presenting a significant challenge in predicting its accuracy. In this paper, an ideal state mechanical model (without eccentricity effects) and an actual state mechanical model (with eccentricity effects) are proposed for the first time to predict the thrust force when back-drilling high-speed printed circuit boards. First, a length model for the effective cutting edge in back-drilling is established for the first time based on back-drilling characteristics. The contact conditions and back-drilling mechanism between the materials (glass fiber-reinforced plastic, resin and copper) and the microdrill (tungsten carbide) are further analyzed in terms of the effective cutting edge and contact mechanics. Then, by considering the eccentricity effects, mechanical models under ideal and actual states are proposed for predicting the thrust forces when back-drilling high-speed PCBs. In addition, by setting different feed rates and spindle speeds and using 4 types of microdrills with different structural parameters, a back-drilling experiment is performed on high-speed PCBs to determine eccentric distances, actual thrust forces, and stub lengths. Compared with the actual thrust force, the maximum error of the ideal model is 8.03%, while the actual model has a better applicability with a maximum error of 5.51% and a minimum error of 1.33%. The experimental results indicate that the thrust force first decreases and then increases as the eccentric distance increases when the chisel edge is involved in the cut during back-drilling. Moreover, the stub length increases with increasing eccentricity and decreasing point angle, while the back-drilling diameter has a negligible effect.

Dual-anchor anti-corrosion coating of copper foil for high-speed interconnects

In this experiment, two similar molecules with bifunctional groups have been characterized to prove the advantages of dual-anchor molecular coating in the interfacial modification of the copper foil. The physicochemical properties of the modified copper foils have been studied. The obtained results indicate that the anti-corrosion performance and peeling strength were significantly improved for the copper foil treated with (2-(Methylthio)pyrimidin-4-yl)methanamine (MET), whose bonding information was analyzed via the density functional theory calculation. It was found that the S-Cu and N-Cu bonds were both formed on the Cu (1 1 1) surface for MET coating, and the adsorption of the double anchor points improves the stability of the interface. The peeling test exhibits the function of MET coating as the adhesion promotor between low-surface profile copper and resin for high-speed signal transmission.

Characterization and Mitigation of Conducted Emissions in a SiC Based Three-Level T-Type Motor Drive for Aircraft Propulsion

This paper presents the full-scale high power inverter design considerations that are needed for minimum conducted noise propagation throughout the system. Specifically, system design issues pertaining to high current and high altitude, high switching transients during commutation process, ribbon cables for high-speed signal transmission, strict conducted emissions requirements and motor side bearing/leakage currents are discussed. Based on the underlying deficits for high power motor drives, layout and circuit design methodologies are proposed to tackle such problems, while keeping costs at a bare minimum. Subsequently, modeling and prediction of common-mode (CM) and differential-mode (DM) noise is made possible using accurate lumped inverter and filter models, allowing for a better understanding of the sensitive components contributing to peak CM-DM noise. A high power (211 kW) rated three level T-type inverter prototype is used to demonstrate the viability of the proposed design techniques for reliable system operation and conducted electromagnetic interference (EMI) emissions mitigation.

Time-Delay Signature Concealment in a Security-Enhanced Optical System With Dual-Loop Electro-Optic Self- Feedback Phase Encryption

In this paper, a novel phase encryption scheme based on a dual-loop electro-optic self-feedback structure is proposed for time-delay signature (TDS) concealment. As for a conventional single-loop feedback structure, the TDS is extremely vulnerable to exposure in the common link, resulting in a fatal weakness in the entire security system, whereas, the introduction of an additional feedback branch, brings about the mutual dynamics between the phase feedbacks, and effectively solves the problem. The modulation depth and dispersion values, which are two crucial variables affecting TDS concealment, are investigated in detail. In principle, the scheme is verified to have better robustness, more security, and can supply large key space. Error-free transmission of high-speed signals is possible. Thanks to the aforementioned benefits, the dual-loop electro-optic structure proposed could inspire fresh ideas for secure optical communication systems in the future.

Low-cost high-speed rapidly reconfigurable integrated half-duplex optical transceiver front-end.

We present and demonstrate an integrated approach to make low-cost high-speed half-duplex optical transceiver with rapid reconfigurability. A single Distributed-Feedback (DFB) diode is employed as the unified E/O-O/E device, which is dynamically biased as laser or photodetector in transmitter or receiver mode. The bias for the DFB and the transmit/receive (T/R) signal path are provided by a custom-designed reconfigurable CMOS chip, which contains the biasing circuitry, a high-speed T/R switch and a burst-mode transimpedance amplifier (BM-TIA). The transceiver front-end operates up to 5 Gb/s for both transmitter (Tx) and receiver (Rx) mode experimentally, while its reconfiguration time is less than 131 ns. This integrated approach not only halves the transceiver optics to facilitate low cost, but also enables high-speed signal transmission as well as rapid reconfiguration, which will be critical for the fiber-to-everything paradigm shift in the near future.

Study on the mechanism affecting the quality of micro-hole in ultrasonic-assisted drilling of high-speed circuit boards

High-speed circuit boards are created to meet the high-speed signal transmission requirements of 5G communication technology, but the non-polar resins, flat glass fibers, and multiple and hard fillers used for this purpose have posed new challenges to their micro-hole processing. The quality of micro-hole has always been a decisive factor in board performance. Therefore, this paper aims at proposing a new processing method for improving the micro-hole drilling quality of high-speed circuit boards. By establishing an ultrasonic-assisted drilling tool motion model, analyzing the changes in drilling method, material deformation, chip breakage, and chip removal during ultrasonic-assisted drilling of printed circuit boards, the influence mechanism on micro-hole quality during ultrasound-assisted drilling is studied prudently. Besides, an experimental platform for ultrasonic-assisted drilling is designed and built, and single-factor experiments for verification of ultrasonic effects, optimization of drilling parameters, and orthogonal experiments for ultrasonic-assisted drilling of high-speed circuit boards are conducted on this platform. The experimental results show that the loading of ultrasonic vibration has made an obvious improvement on several machining defects including hole wall roughness, entrance burr, and nail head in micro-hole drilling of high-speed circuit boards. In addition, the influence order of each processing parameter and a better combination of them are discovered, which provides a theoretical research basis and instructions for the improvement of micro-hole quality of high-speed circuit boards.

Supercritical carbon dioxide foaming for ultra-low dielectric loss perfluorinated foam

Microelectronic is developing towards high frequency (GHz) and high speed (Gpbs), putting forward high requirements for low dielectric materials. The most efficient method for fabricating low dielectric materials is the incorporation of air into matrix via supercritical CO2 foaming. Herein, a low dielectric thermoplastic perfluorinated polymer is selected to be the matrix and another low dielectric perfluorinated polymer which is capable to form in-situ nanofibrils is selected to regulate the matrix viscoelasticity. Supercritical CO2 foaming method is then applied to introduce a large amount of low dielectric air into nanofibrill modified perfluorinated polymer. Owing to supercritical CO2 as a residue-free foaming agent (residue impurities in matrix originated from foaming agent would increase dielectric loss significantly at GHz) and its strong interaction with perfluorinated polymer (ensure large expansion ratio of the obtained foams to introduce a large amount of low dielectric air in matrix), the lowest dielectric loss of 0.00015 (among the existing polymeric materials) is then obtained by supercritical CO2 foaming of in-situ nanofibril modified perfluorinated polymer. Furthermore, the hydrophobic and oilphobic properties of the perfluorinated polymer were enhanced by supercritical CO2 foaming to form a cellular structure; simultaneously, the corrosion resistance to strong alkali and V0 flame retarding properties of the ultra-low dielectric foam were maintained resulted from the perfluorinated cell walls. Therefore, such superior comprehensive performance of this ultra-low dielectric perfluorinated foam made from supercritical CO2 foaming enables it the best alternative for the next-generation high-frequency (GHz to THz) and high-speed (sub Tbps) signal transmission substrate in electronics.

A Review on Materials and Methods for the Fabrication of Microcavity Laser

Optical microcavities are resonators that have at least one dimension on the order of a single optical wavelength. These structures enable one to control the optical emission properties of materials placed inside them. One of their most dramatic potential features is threshold-less lasing,unlike the conventional lasers. This is possible due to 2D monolayers, Heterostructures, Hybrid materials which are used as active layers for polariton-exciton strong coupling. In this review paper, a different method of Microcavity laser fabrication is reviewed, where a different type of active materials is utilized to improve the laser efficiency. Materials such as WS2, MoS2, WSe2 and MoSe2are used due to their strong exciton binding energy. These use high reflecting DBR mirrors fabricated using oxides of a higher refractive index such as SiO2, NbO2, HfO2/Al2O3, SiO2/Ta2O5 and SiO2/TiO2. In this way, the controlled spontaneous emission is expected to play a vital role in a new generation of optical devices and can have a wide range of applications in Optics, Quantum computing, high-speed signal transmission, etc.

System Scaling on High Speed Signal Transmission

System Scaling on High Speed Signal Transmission

High-throughput finite-element design of dielectric composites for high-frequency copper clad laminates

Dielectric substrates with low dielectric constant and good thermal stability are highly desired for high-frequency and high-speed signal transmission. It is however challenging to rationally design the demand-satisfied polymer-based composites due to the inadequate understanding of the contradictory effect of inorganic fillers on modulating dielectric-thermal-mechanical properties. In this work, taking Polytetrafluoroethylene (PTFE)-SiO2 composite as the example, we perform high-throughput finite-element calculations to systematically study the filler effects on the dielectric constant of composites εrcomposite and the coefficient of thermal expansion of composites (CTE-c). A series of influencing factors including intrinsic property, volume fraction, shape, distribution, and orientation of fillers have been considered in our models to establish the structure-property mapping of dielectric composites. It is found that CTE-c is more sensitive to the filler structure of PTFE-SiO2 composites than εrcomposite. Finally, guided by the calculation results, a skeleton structure is proposed to realize the performance targets of εrcomposite< 2.3 and CTE-c < 60 ppm/K with lower SiO2 filler content. This work provides a universal data-driven strategy for the rational design of dielectric composites with multi-objective requirements, and it is expected to spark more experimental efforts to design novel dielectric composites for high-quality signal transmission.

분할 공동 구조를 이용한 고 종횡비 인쇄회로기판 내 전송선 층 변환 구조의 신호 무결성 개선 설계 및 모델링

This paper proposed a layer transition design for high-speed signal transmission in high aspect ratio printed circuit boards (PCBs). The proposed design employed a segmented cavity structure to suppress the group cavity resonance that degrades a wide bandwidth range of high-speed transmission lines with signal vias for layer transition. To predict the transfer characteristic of the proposed design, equivalent circuit models were developed based on the combination of resonant cavity models, lumped via models, and conventional transmission line models. The proposed design and equivalent circuit models were validated with a noticeable improvement in the signal integrity performance by simulation and measurement results up to 30 GHz.

Modulation Method for High-Capacity Fibre Channel Switch and High-Speed Pulse Network Data

Fibre channel (FC) switches are widely used in storage area networks and avionics systems. In this work, the FC protocol, the switching structure and the scheduling algorithm of the FC switch are deeply studied, and a 48-port FC switch is completed on a single-chip field-programmable gate array (FPGA). In addition, an improved scheduling algorithm for Inter-System Link Protocol (iSLP) is proposed for the input and scheduling of optical fiber pulse network data. On this basis, the overall architecture of the FC switch is proposed, the x690tffg1158 FPGA chip is selected, and the FC port control module is designed, which is composed of the receiving controller, the interface state machine, the sending controller, and the flow control. The routing table lookup module of FC switch is designed, the unicast routing table format and multicast routing table format are proposed, and the corresponding unicast and multicast routing table lookup table module architectures are designed. Aiming at the characteristics of high reliability and low distortion in the transmission of high-speed pulse network signals by FC switches, the modulation and demodulation of Bias-T (BIAS-T) are redesigned. The experiment is implemented using Verilog hardware description language (HDL), and Modelsim 10.5 software is adopted to simulate each module of the switch. The switch adopts an 8×N switching structure, which can accurately perform word synchronization. After the link is initialized, the transceivers can send and receive data frames normally. The redesigned BIAS-T is applied to solve the instability of the end of the analog modulation method, and then realize the low distortion and data integrity of the high-speed pulse signal of the FC switch.

Evaluation of High-Speed Link Parameters for Highly Reliable Reconfigurable Systems Based on S-Parameters and BER

Purpose of research. is to improve signal transmission parameters in high-speed signal transmission lines, including between programmable logic integrated circuits (PLIC). This improvement in signal transmission parameters is necessary to increase throughput of modern highly reliable reconfigurable systems to ensure data transfer rate of up to tens of Gbit/s. It can be done considering the influence of electrical and structural parameters of multi-layer printed circuit boards (MPCB) on them. It is possible to provide such high data rates by using a wider frequency band of transmitted signals. One of the existing approaches to this problem is to increase "physical" frequency of transmitted information signals to 25-300 GHz, which is sufficient to achieve desired rates.Methods. A method for estimating quality of high-speed signal transmission lines based on the definition of standardized methods for analyzing signal transmission parameters, such as JCOM, S-parameters and BER is proposed in the article. This method allows evaluating high-speed communication lines. Thus, the Channel Operating Margin (COM)/JCOM parameter can be used to estimate the quality of a digital communication channel - a standardized method for determining the overall channel quality indicator. Known methods are used to estimate such signal transmission parameters as S11 reflection coefficient and S21 attenuation coefficient (S-Parameters). These methods are used to estimate attenuation and loss of the information signal in the path, when copies of the signal reflected from inhomogeneities affect the original and lead to its distortion. Simulation of such parameter as Bit Error Rate (BER) is carried out according to G.821/G.826/M2100 rationing and quality control methodology.Results. The main metrics were selected to evaluate the quality of high-speed signal transmission lines. It is based on the evaluation of such signal transmission parameters as Channel Operating Margin (COM), S-parameters and Bit Error Rate (BER). Numerical evaluations of signal transmission parameters were obtained and their effect on the design parameters of high-speed signal transmission lines was estimated. It is recommended to use at least 1 transition hole between screening polygons in GND separation layers every 0.5 cm or 0.25 cm2 of WFP area. It is for a data rate of less than 25 Gbit/s, It is recommended to use at least 2 transition holes between screening polygons in GND separation layers every 0.5 cm or 0.25 cm² of PV area, if high-speed signal transmission line passes at a distance of closer than 2.5 cm from the power supply circuits in a projection on the layer where the power supply circuits are located.Conclusion. A method for calculating signal transmission parameters on high-speed signaling lines based on the calculation of Channel Operating Margin (COM), S-parameters and Bit Error Rate (BER) parameters is introduced. As part of introduced method, an analysis of signal transmission parameters was carried out. This analysis shows that when the "reference" values of electrical parameters of the line are met, the transfer holes contribute most to the signal distortion; then the layers in which the signal line is located, the number of screening polygons between the signal layers and the layers; in which the power supply circuits, the design parameters of the transition holes, as well as the length and number of segments of the high-speed line pass. Numerical evaluations of minimum number of transition holes and their diameter, the length of segments of differential pairs are given. These results can be used in pre-layout analysis step of high-speed signal transmission lines for computational modules of highly reliable reconfigurable systems.