High Speed Serial Data Transmission Research Articles

Design and Simulation of HiGBt, a 5 Gb/s SerDes for Heavy-Ion Physics Experiments

The Heavy Ion Research Facility on Lanzhou (HIRFL) and the High-Intensity heavy-ion Accelerator Facility (HIAF) are the leading heavy-ion physics centers. The increased scale of physics experiments at HIRFL and HIAF has put forward urgent requirements on high-speed serial data transmission links. Also, the intense radiation environment is a significant challenge to commercial ASIC. This paper presents the HiGBt, a general-purpose 5 Gbps SerDes ASIC designed in a 0.13 μm CMOS process for data transmission at HIRFL and HIAF. The HiGBt mainly consists of a Serializer, a Deserializer, and a high-speed clock system. The Serializer includes three stages to realize high-speed serialization. The Deserializer adopts a high linearity phase-interpolator-based structure to avoid coupling multi-VCOs. Finally, the high-speed clock system has a Single Event Upsets (SEUs)-protected divider. The simulation results indicate that the power consumption of the SerDes is 146.3 mW, while the layout area is 310 μm × 310 μm.

THE EYE OPENING IMPROVEMENT METHOD FOR A HIGH SPEED CURRENT MODE LOGIC DRIVER

A bandwidth improvement method of current mode logic (CML) drivers, of the integral circuit type specifically designed for high-speed serial data transmission systems is presented. These drivers are characterized by their ability to operate at high frequencies and their ability to provide a high level of signal integrity, which is critical for achieving high data rates and low error rates in high-speed systems. The key advantages of CML drivers such as providing a high level of signal integrity, the circuit topologies, operating modes, and performance characteristics are discussed. Furthermore, the challenges and limitations of CML drivers, as well as the recent advances in the field that enables the use of CML drivers in high-speed systems are also discussed. A driver constructed by the proposed method operating at 112 Gbps in PAM4 modulation consumes 9 mW under 0.9 V supply.

High-Speed Serial Data Transmission Error Control Based on Fuzzy Classification

At present, the error control method for high-speed serial data transmission obtains the errors by comparison and then controls them. If the data transmission channel is not denoised, the packet loss and error codes become serious, and energy consumption increases. The use of fuzzy classification is proposed to control data transmission errors. The method uses the combination of wavelet transform and transform domain difference to double denoise the channel, and it completes the clustering of data transmission errors by fuzzy classification. Considering packet loss, error codes, and energy consumption in data transmission error control, when the communication distance between two nodes is small, automatic repeat request is used to control data transmission errors. As the distance between nodes increases, forward error correction is used to control data transmission errors. When the communication distance gradually increases, data transmission errors are controlled by hybrid automatic repeat request. Experiments showed that the proposed method can reduce the data transmission error, control energy consumption, packet loss rate, and bit error rate, and enhance the denoising effect.

Development and Implementation of Parallel to Serial data Transmitter Using Aurora Protocol for High Speed Serial Data Transmission on Virtex-7 FPGA

The objective of this paper is Development and Implementation of parallel to serial data converter using Aurora protocol for high speed serial data transmission at the rate of 3.125Gbps by using architectural features of Virtex-7 FPGA. It involves the study and configuring the Xilinx Core Generator Tool to achieve the required high speed serial data transmission by using of Aurora 8b/10b Protocol & Multi-Gigabit Transceivers present in Virtex-7 FPGA. Firstly, a 192-bit parallel data is generated using simulators, which is implemented using VHDL language. The 192-bit data is sent to Asynchronous First-In First-Out (AFIFO) as input and produces an output of 32-bit parallel data. This data is sent to the aurora module in parallel form as successive frames (i.e. 6 frames, each frame consists of 4 bytes). Finally, the 192-bit parallel data is transmitted to the receiver module serially over fiber optic cable at the rate of 3.125Gbps using architectural features of virtex7 FPGA. Finally, the data is transmitted on dual independent aurora channels and the entire logic will be tested for its complete functionality in standalone mode by porting on to the Virtex-7 FPGA based custom Hardware. Keywords: Aurora Protocol, Independent Aurora Channels, Serial Data Transmission, Virtex-7 FPGA, AFIFO, GTX TILE, MGT’s

A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks

Duobinary modulation is a robust and attractive coding format for high-speed serial data transmission because it allows an excellent tradeoff between speed, noise and power. However, conventional architectures reported in the literature performing the necessary precodification in a duobinary transceiver suffer from a severe vulnerability to glitches that limits their performances at high data rates. This study presents a new precoder scheme that overcomes this limitation with a very small design, area and power consumption, and a time-domain analysis that confirms the advantages of the proposed solution. The proposed precoder has been implemented in a full duobinary transceiver fabricated in a 0.13-μm partially depleted-silicon on insulator CMOS technology that works at 10 Gb/s. The fabricated precoder consumes 13.8 mW and the decoder consumes 23.2 mW from a single supply of 1.2 V. Experimental results are provided for a simulated channel of 50-m plastic optical fiber.

Improved Precoder Architecture for Duobinary Transceivers

Duobinary modulation is an attractive baseband modulation scheme for high-speed serial data transmission. This work presents a duobinary transceiver with a new precoder architecture that overcomes the glitch vulnerability of the conventional ones. It has been fabricated in a 0.13-μm PD-SOI CMOS technology and achieves 10 Gbps consuming 37 mW.

Application of High Speed Serial Data Transmission System in Remote Sensing Camera

In order to meet the system needs of miniaturization, real-time, high-speed data and high reliability transmission in remote sensing camera, a high-speed serial protocol based on high-speed serial/parallel converter SerDes is proposed. For the SerDes high-speed serial data transmission chip for the physical layer, FPGA for the link layer of the communication system, design high-speed serial transmission communication protocol. Through the development of a simplified protocol for the upper user to provide a simple data interface. The system completed the data rate of 12.5Gbps point to point high-speed transmission. Verification is done by sending a pseudo-random code between boards. System work 3 hours, the measured bit error rate is less than 10 -12 .

Low-latency and low-overhead encoder ASIC in the ATLAS LAr calorimeter trigger upgrade

ABSTRACTIn this article, an encoder Application Specific Integrated Circuit (ASIC) for high-speed serial data transmission is presented. The ASIC implements a low-latency and low-overhead line code and is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. The ASIC operates at 640 MHz with a latency of no greater than 6.25 ns and the overhead of 14.3%. The encoder will be integrated with a serialiser and will be used in the A Toroidal LHC ApparatuS Liquid Argon (LAr) calorimeter Phase-I trigger upgrade.

Design of 12B/14B: A Novel SERDES Encoding Technique

In satellite systems, large amount of high speed data is required to be transmitted from one system to another. Conventional parallel data transmission requires a large number of cables/interface-packages and results in large weight and volume. Parallel interface in a typical future camera system requires >8000 cables between camera electronics and data handling system. In addition, with increase in transmission rate, problems associated with crosstalk become more critical. One possible solution identified is serial interface, also termed as SERDES (SERializer/DESerializer) interface. A typical SERDES interface comprises of encoder/decoder, PLL, timing- control and multiplexer/de-multiplexer. Encoding of serial data solves high speed serial data transmission problems by incorporating clock embedding, DC balancing, sync info insertion and error detection. DC balancing also solves the issue of Inter-Symbol Interference (ISI). Available SERDES interface devices have limitations like poor reduction factor, no clock embedding or non-availability of space qualified part. Hence, an attempt is made to understand and implement SERDES encoder/decoder with a goal of indigenous SERDES ASIC development. Due to 12-bit input interface, a novel 12B/14B encoding technique is designed and developed. The developed technique preserves many good properties widely used 8B/10B encoding technique. FPGA simulation results achieved >50MSPS parallel rate which will lead to >700 Mpbs serial rate. Developed technique is very efficient and suitable for onboard implementation. Index Terms—SERDES, BER, 8B/10B, Disparity, DC-balance, AC-coupled, Run-length

A prototype of trigger electronics for LAWCA experiment

The Large Area Water Cherenkov Array (LAWCA) experiment focuses on high energy gamma astronomy between 100 GeV and 30 TeV. Invoked by the idea of hardware triggerless structure, a prototype of LAWCA trigger electronics is implemented in one single VME-9U module which obtains all the data from the 100 Front End Electronic (FEE) endpoints. Since the trigger electronics accumulate all the information, the flexibility of trigger processing can be improved. Meanwhile, the dedicated hardware trigger signals which are fed back to front end are eliminated; this leads to a system with better simplicity and stability. To accommodate the 5.4 Gbps system average data rate, the fiber based high speed serial data transmission is adopted. Based on the logic design in one single FPGA device, real-time trigger processing is achieved; the reprogrammable feature of the FPGA device renders a reconfigurable structure of trigger electronics. Simulation and initial testing results indicate that the trigger electronics prototype functions well.

ASIC developments for high speed serial data transmission in particle physics experiments

We report R&D results on two integrated circuit designs: a 5Gbps 16:1 serializer and a 5GHz LC phase-locked-loop (PLL). The prototypes were fabricated with a commercial thin-film silicon-on-sapphire 0.25μm CMOS technology. Both the serializer and the PLL have been evaluated to meet design goals and tested against operation conditions in the environment of a particle physics detector front-end for the proposed HL-LHC upgrade.

Modeling and Design Optimization of a Wideband Passive Equalizer on PCB Based on Near-End Crosstalk and Reflections for High-Speed Serial Data Transmission

We propose a closed-form analytic model for the newly presented passive equalizer using near-end crosstalk and reflections on printed circuit board (PCB). The proposed model is developed by using impulse response analysis and the Fourier transform. Based on the model, we propose a design-optimization procedure for the passive equalizer, which achieves eye-opening maximization and ISI minimization in order to maximize the equalization performance and reduce the design cycle. In the proposed optimization procedure, the eye-opening is maximized with a parameter sweep and peak distortion analysis, and the ISI is minimized by the proposed negative ISI cancellation technique. The proposed model and the design-optimization procedure are demonstrated experimentally for a data rate of 16 Gb/s on a 40-cm-long backplane PCB, and they achieve wideband equalization with a significant improvement in the voltage and timing margins of the received serial data.

52 Gb/s 161 transmitter in 0.13 [micro sign]m SiGe BiCMOS technology

A52-Gb/s 16:1 quarter-rate clocking transmitter for high-speed serial data transmission is designed to utilise 0.13-mum SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The quarter-rate transmitter consists of a 16:1 multiplexer (MUX), a voltage-controlled ring oscillator, a phase-locked loop (PLL), a pseudorandom data generator and an output amplifier. The voltage-controlled ring oscillator has a wide tuning range from 11 to 22 GHz with feedforward loop and delay interpolation. A continuous model of a third-order PLL is developed and used to optimise loop filter parameters and to estimate the PLL performance in a simulation. The PLL achieves a low phase noise of -124.6 dBc/Hz at 1 MHz offset. The 16:1 MUX features quarter-rate clock multiplexing with multi-phase voltage-controlled oscillator clocks. In the design of a 16:1 MUX, an edge-channelling 4:1 MUX is used to alleviate a duty cycle and a jitter problem.