Abstract
The Heavy Ion Research Facility on Lanzhou (HIRFL) and the High-Intensity heavy-ion Accelerator Facility (HIAF) are the leading heavy-ion physics centers. The increased scale of physics experiments at HIRFL and HIAF has put forward urgent requirements on high-speed serial data transmission links. Also, the intense radiation environment is a significant challenge to commercial ASIC. This paper presents the HiGBt, a general-purpose 5 Gbps SerDes ASIC designed in a 0.13 μm CMOS process for data transmission at HIRFL and HIAF. The HiGBt mainly consists of a Serializer, a Deserializer, and a high-speed clock system. The Serializer includes three stages to realize high-speed serialization. The Deserializer adopts a high linearity phase-interpolator-based structure to avoid coupling multi-VCOs. Finally, the high-speed clock system has a Single Event Upsets (SEUs)-protected divider. The simulation results indicate that the power consumption of the SerDes is 146.3 mW, while the layout area is 310 μm × 310 μm.
Published Version
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