High-speed Printed Circuit Boards Research Articles

Investigation on the new reliability issues of PCB in 5G millimeter wave application

PurposeThe purpose of this paper is to illustrate the new technical demands and reliability challenges to printed circuit board (PCB) designs, materials and processes when the transmission frequency increases from Sub-6 GHz in previous generations to millimeter (mm) wave in fifth-generation (5G) communication technology.Design/methodology/approachThe approach involves theoretical analysis and actual case study by various characterization techniques, such as a stereo microscope, metallographic microscope, scanning electron microscope, energy dispersive spectroscopy, focused ion beam, high-frequency structure simulator, stripline resonator and mechanical test.FindingsTo meet PCB signal integrity demands in mm-wave frequency bands, the improving proposals on copper profile, resin system, reinforcement fabric, filler, electromagnetic interference-reducing design, transmission line as well as via layout, surface treatment, drilling, desmear, laminating and electroplating were discussed. And the failure causes and effects of typical reliability issues, including complex permittivity fluctuation at different frequencies or environments, weakening of peel strength, conductive anodic filament, crack on microvias, the effect of solder joint void on signal transmission performance and soldering anomalies at ball grid array location on high-speed PCBs, were demonstrated.Originality/valueThe PCB reliability problem is the leading factor to cause failures of PCB assemblies concluded from statistical results on the failure cases sent to our laboratory. The PCB reliability level is very essential to guarantee the reliability of the entire equipment. In this paper, the summarized technical demands and reliability issues that are rarely reported in existing articles were discussed systematically with new perspectives, which will be very critical to identify potential reliability risks for PCB in 5G mm-wave applications and implement targeted improvements.

Mechanical model of back-drilling high-speed printed circuit boards with eccentricity effects

The rapid development of fifth-generation (5 G) communication technology is placing greater demands on the performance of high-speed printed circuit boards (PCBs). Back-drilling plays a crucial role in achieving high-frequency and high-speed signal transmission and is a key technology for improving the signal integrity of high-speed PCBs. The thrust force is considered the main factor affecting hole quality when drilling PCBs. Accurately predicting the thrust force is essential for optimizing the back-drilling process. However, back-drilling thrust force is strongly coupled with eccentricity, presenting a significant challenge in predicting its accuracy. In this paper, an ideal state mechanical model (without eccentricity effects) and an actual state mechanical model (with eccentricity effects) are proposed for the first time to predict the thrust force when back-drilling high-speed printed circuit boards. First, a length model for the effective cutting edge in back-drilling is established for the first time based on back-drilling characteristics. The contact conditions and back-drilling mechanism between the materials (glass fiber-reinforced plastic, resin and copper) and the microdrill (tungsten carbide) are further analyzed in terms of the effective cutting edge and contact mechanics. Then, by considering the eccentricity effects, mechanical models under ideal and actual states are proposed for predicting the thrust forces when back-drilling high-speed PCBs. In addition, by setting different feed rates and spindle speeds and using 4 types of microdrills with different structural parameters, a back-drilling experiment is performed on high-speed PCBs to determine eccentric distances, actual thrust forces, and stub lengths. Compared with the actual thrust force, the maximum error of the ideal model is 8.03%, while the actual model has a better applicability with a maximum error of 5.51% and a minimum error of 1.33%. The experimental results indicate that the thrust force first decreases and then increases as the eccentric distance increases when the chisel edge is involved in the cut during back-drilling. Moreover, the stub length increases with increasing eccentricity and decreasing point angle, while the back-drilling diameter has a negligible effect.

Tree-Based Machine Learning Models with Optuna in Predicting Impedance Values for Circuit Analysis.

The transmission characteristics of the printed circuit board (PCB) ensure signal integrity and support the entire circuit system, with impedance matching being critical in the design of high-speed PCB circuits. Because the factors affecting impedance are closely related to the PCB production process, circuit designers and manufacturers must work together to adjust the target impedance to maintain signal integrity. Five machine learning models, including decision tree (DT), random forest (RF), extreme gradient boosting (XGBoost), categorical boosting (CatBoost), and light gradient boosting machine (LightGBM), were used to forecast target impedance values. Furthermore, the Optuna algorithm is used to determine forecasting model hyperparameters. This study applied tree-based machine learning techniques with Optuna to predict impedance. The results revealed that five tree-based machine learning models with Optuna can generate satisfying forecasting accuracy in terms of three measurements, including mean absolute percentage error (MAPE), root mean square error (RMSE), and coefficient of determination (R2). Meanwhile, the LightGBM model with Optuna outperformed the other models. In addition, by using Optuna to tune the parameters of machine learning models, the accuracy of impedance matching can be increased. Thus, the results of this study suggest that the tree-based machine learning techniques with Optuna are a viable and promising alternative for predicting impedance values for circuit analysis.

Inductance Calculation for the Power Net Area Fill of Packages and PCBs Based on Plane-Pair PEEC

The inductance of the power/ground planes is an integral contributor to the input impedance of a power delivery network for high-speed printed circuit boards (PCBs) and packages. Conventionally, differential-equation (DE) circuit and cavity type models have been applied to compute the inductive behavior of the plane-to-plane inductance. However, these methods are not suitable for the case where the structures are perforated or involve other uneven structures. In this article, a new partial-element-equivalent-circuit (PEEC)-based method is presented to compute the inductance of parallel plate-like planes and other structures. Examples are given to show that the new method can efficiently compute inductances for multiple integrated circuit power vias, power/ground planes, and multiple decoupling capacitors. The proposed model is validated with both full-wave CEM simulations as well as with measurements. Further, the speed and the accuracy for real PCB and package designs are presented to validate the efficiency as well as the accuracy of the proposed approach. An important aspect of any approach is the limitations for solving real life problems. In this article, we consider important issues related of plane-pair PEEC to power distribution evaluations. Specifically, we show that large holes in planes can accurately be modeled. This is a difficult issue for DE methods. Another surprising practical issue is the accuracy obtained even if the planes are not of the same size. We also consider the speedup, which can be obtained in comparison to solutions for other approaches. This is due to the sparsity of the coupling for the rapid coupling decrease with distance. This short-distance coupling also increases the maximum frequency for which the method can be applied.

Chemical bonding of copper and epoxy through a thiol-based layer for post 5G/6G semiconductors

With the development of post 5G/6G high-speed communication, the current frequency in the substrate is increasing. A flat copper substrate surface is wanted to reduce the signal loss caused by the skin effect. However, a flat surface harms the bonding strength between copper and epoxy, resulting in poor reliability for printed circuit boards (PCBs). This work tried to improve the bonding strength between a flat copper surface and an epoxy by bonding copper and epoxy chemically via 4-aminothiophenol (4-ATP). We investigated the influence of the treatment time of copper in a 2 mM 4-ATP ethanol solution. The treated surfaces were characterized by SEM, IRRAS, Raman, AFM, and XPS. In addition, we compared the experimental XPS results with the simulated XPS spectrum obtained via Simulation of Electron Spectra for Surface Analysis (SESSA) software, enabling us to understand the treated surface quantitatively. The interaction between treated cooper surface and epoxy was analyzed via Density Function Theory (DFT). The best treatment time is 1 h. Under this condition, the shear strength between copper and epoxy improved from 8.2 MPa to 24.1 MPa. The processing and bonding mechanisms were discussed. The results are expected to contribute significantly to fabricating of high-speed communication PCBs.

Effects of Coating Parameters of Hot Filament Chemical Vapour Deposition on Tool Wear in Micro-Drilling of High-Frequency Printed Circuit Board

High-frequency and high-speed printed circuit boards (PCBs) are made of ceramic particles and anisotropic fibres, which are difficult to machine. In most cases, severe tool wear occurs when drilling high-frequency PCBs. To protect the substrate of the drills, diamond films are typically fabricated on the drills using hot filament chemical vapour deposition (HFCVD). This study investigates the coating characteristics of drills with respect to different HFCVD processing parameters and the coating characteristics following wear from machining high-frequency PCBs. The results show that the methane concentration, processing time and temperature all have a significant effect on the grain size and coating thickness of the diamond film. The grain size of the film obviously decreases as does the methane concentration, while the coating thickness increases. By drilling high-frequency PCBs with drills with nanocrystalline and microcrystalline grain sizes, it is discovered that drills with nanocrystalline films have a longer tool life than drills with microcrystalline films. The maximum length of the flank wear of the nanocrystalline diamond-coated drill is nearly 90% less than microcrystalline diamond-coated tools. Moreover, drills with thinner films wear at a faster rate than drills with thicker films. The findings highlight the effects of HFCVD parameters for coated drills that process high-frequency PCBs, thereby contributing to the production of high quality PCBs for industry and academia.

Back-drilling of high-speed printed circuit boards: a review

Back-drilling of high-speed printed circuit boards: a review

A Method of Optimizing Characteristic Impedance Compensation Using Cut-Outs in High-Density PCB Designs.

The modern era of technology contains a myriad of high-speed standards and proprietary serial digital protocols, which evolve alongside the microwave and RF realm. The increasing data rate push the requirements for hardware design, including modern printed circuit boards (PCB). One of these requirements for modern high-speed PCB interfaces are a homogenous track impedance all the way from the source to the load. Even though some high-speed interfaces don’t require any external components embedded into the interconnects, there are others which require either passive or active components—or both. Usually, component package land-pads are of fixed size, thus, if not addressed, they create discontinuities and degrade the transmitted signal. To solve this problem, impedance compensation techniques such as reference plane cut-out are employed for multiple case studies covering this topic. This paper presents an original method of finding the optimal cut-out size for the maximum characteristic impedance compensation in high-density multilayer PCB designs, which has been verified via theoretical estimation, computer simulation, and practical measurement results. Track-to-discontinuity ratios of 1:1.75, 1:2.5, and 1:5.0 were selected in order to resemble most practical design scenarios on a 6-layer standard thickness PCB. The measurements and simulations revealed that the compensated impedance saturation occurs at (150–250%) cut-out widths for a 50 Ω microstrip.

Meander-DGS Effect on Electromagnetic Bandgap Structure for Power/Ground Noise Suppression in High-Speed Integrated Circuit Packages and PCBs

In this paper, we present the impact of a meander-shaped defected ground structure (MDGS) on the slow-wave characteristics of a lowest-order passband and a low cutoff frequency of the first stopband of an electromagnetic bandgap (EBG) structure for power/ground noise suppression in high-speed integrated circuit packages and printed circuit boards (PCBs). A semi-analytical method is presented to rigorously analyze the MDGS effect. In the analytical method, a closed-form expression for a low cutoff frequency of the MDGS-EBG structure is extracted with an effective characteristic impedance and a slow-wave factor. The proposed analytical method enables the fast analysis of the MDGS-EBG structure so that it can be easily optimized. The analysis of the MDGS effect revealed that the low cutoff frequency increases up to approximately 19% while comparing weakly and strongly coupled MDGSs. It showed that the miniaturization of the MDGS-EBG structure can be achieved. It was experimentally verified that the low cutoff frequency is reduced from 2.54 GHz to 2.00 GHz by decreasing the MDGS coupling coefficient, which is associated with the miniaturization of the MDGS-EBG structure in high-speed packages and PCBs.

Skin Effect and its Impact on Resistance of Conductor Traces in High Speed Printed Circuit Board Design.

Skin Effect and its Impact on Resistance of Conductor Traces in High Speed Printed Circuit Board Design.

Tribological performance and wear mechanism of smooth ultrananocrystalline diamond films

• HFCVD is used to synthesize UD-MCD, UD-UNCD, UD-MCD/UD-UNCD, BD-MCD, BD-UNCD, BD-MCD/BD-UNCD films on WC-Co substrates. • Growth mechanism of UNCD with high carbon concentration and low gas pressure in hydrogen-rich chemistry are illustrated. • Undoped and boron doped UNCD coatings are firstly applied on WC-Co micro drills to improve the surface smoothness. • Both boron doping and middle layer MCD contribute to the strong adhesive level of UD-MCD/UD-UNCD and BD-MCD/BD-UNCD. • The UD-MCD/UD-UNCD, BD-UNCD and BD-MCD/BD-UNCD coated PCB micro drills show superior cutting performances. 5G printed circuit boards (PCBs), composed of glass fiber, epoxy resin and ceramic, are a kind of difficult-to-machine material. The manufacture of massive high-quality micro holes on 5G PCBs raise high requirements on the tool life and machining precision of PCB micro drills. Chemical vapor deposition (CVD) diamond coatings can be used as effective protective films on PCB micro drills. The surface smoothness and coating-substrate adhesion of diamond coated micro drills are two important factors affecting the drilling performances. Different from previously reported microcrystalline diamond (MCD) or nanocrystalline diamond (NCD) coating types on cutting tools, undoped (UD-) and boron doped (BD-) ultrananocrystalline diamond (UNCD) coatings with higher surface smoothness are firstly applied on PCB micro drills to reduce the friction and cutting resistance and improve the cutting performances while machining PCBs. Moreover, different from the usual argon-rich gas atmosphere for UNCD synthesis, the synthesis mechanisms of UD-UNCD and BD-UNCD with hydrogen-rich atmosphere adopting HFCVD method are clarified. Sufficiently high renucleation rate of diamond crystallites, long mean free path of reactive precursor species and high removal rate of non-diamond carbon phases lead to the successful synthesis of UNCD films. UDMCD, UD-UNCD, UD-MCD/UD-UNCD, BD-MCD, BD-UNCD, and BD-MCD/BD-UNCD, were synthesized on PCB micro drills using HFCVD. The tribological performances and wear mechanisms of these different diamond coatings were studied systematically. The dominant wear mechanism causing tool wear and fracture of diamond coated micro drills in high-speed machining PCBs is abrasive wear. The degree of abrasive wear while machining PCBs are mainly determined by the surface smoothness, surface roughness and coefficient of friction of diamond coatings. The top layer UNCD with tiny grain size leads to the improvement of surface smoothness and tribological properties, which enhance the chip evacuation capacity and reduce the tool wear. Besides, both boron doping and middle layer MCD can contribute to the strong coating-substrate adhesion. Therefore, BD-MCD/BD-UNCD coated micro drill exhibits the best cutting performances while machining PCBs.

A Novel Double-Square Electromagnetic Bandgap Structure for Wideband SSN Suppression in High-Speed PCB

In this article, a novel double-square planar electromagnetic bandgap structure for suppressing wideband simultaneously switching noises is proposed. The equivalent circuit model for its periodic structure design is carefully developed and analyzed for the function as a band-stop filter. The performance of the circuit model is experimentally verified and lower cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> ) can be effectively predicted, while keeping the compact size of the structure. Two test boards are fabricated and the measurement results show that the noise suppression performance can reach -30 dB between two adjacent ports from 3.2 to 21.2 GHz. To prove the solid signal transmission quality of the proposed structure in high-speed printed circuit board, feasibility studies on eye patterns are conducted at four different coded rates. All the performance results and the comparison with other works show its salient feature of solid signal integrity in both the frequency and time domains.

High-Speed Printed Circuit Boards: A Tutorial

Circuit designers often tend to overlook Printed Circuit Board (PCB) designs. Circuits performance and the quality of measurements, however, are strongly correlated with careful and comprehensive PCB design techniques. Such design techniques are applicable to practically all circuits areas including analog, digital, RF, and power applications. This paper provides a fundamental understanding of common problems faced in designing high-performance and high-speed PCBs. While this tutorial paper does not cover basics of PCBs, it presents empirical and commonly practiced methods to deliver professional layouts. This includes studying on-board transmission lines and their matching techniques, various PCB structures that ensure good signal integrity, and bypass capacitors, for circuits up to 30 GHz. Conclusions and suggestions are justified with theoretical analysis and supported by simulations and measurements.

A 12.5 Gb/s 1.93 pJ/Bit Optical Receiver Exploiting Silicon Photonic Delay Lines for Clock Phases Generation Replacement

This brief describes a high-speed optoelectronic receiver implemented in 65 nm CMOS technology. The receiver utilizes only two clock phases instead of the four conventionally used in a quarter-rate clocking system. This two-clock phase system is enabled by a passive silicon photonic split and delay structure that eliminates the need for a quadrature clock phase generator and all the associated buffers. Moreover, the outputs of the receiver are demultiplexed which further helps reducing power consumption in the digital part of the system. The receiver also employs inter-stage AC coupling and is mounted on a high-speed printed circuit board (PCB). The impact of AC coupling and PCB parasitics is investigated. The functionality of the receiver is validated by high-speed optical measurements. The receiver achieves an error-free transmission (BER < 10−12) up to a data rate of 12.5 Gb/s with an energy efficiency of 1.93 pJ/bit and sensitivity of −4 dBm from a 1 V supply.

Suppression of Wideband Simultaneous Switching Noise Through Application of a Partial Electromagnetic Band-Gap Structure in Multilayer Printed Circuit Boards

Adding mushroom-like electromagnetic band-gap (EBG) structures to split power planes can produce wideband suppression of ground bounce noise in high-speed printed circuit boards. Practical equations are used to estimate the stop-band performance of EBG structures within parallel power planes. In this article, a mushroom-like EBG and power-bus structure are derived using the modified nodal analysis (MNA) method. Equations calculated using the MNA method are easily programmable. The partial EBG structures developed in this article can suppress noise from electromagnetic (EM) interference within parallel plates in the power bus. Several examples below show that similar results can be obtained in measurements, in EM simulations software, and in derived equations. The proposed structure enhanced the suppression of simultaneous switching noise coupling (≤-40 dB) within the range of 260 MHz to 10 GHz.

A novel electromagnetic bandgap design applied for suppression of printed circuit board electromagnetic radiation

In this article, a novel electromagnetic bandgap structure is applied to a high-speed printed circuit board, where the proposed concept is to etch with traditional L-bridge and extended connecting branches on the power plane. To investigate the electromagnetic characteristics of the proposed structure, its transmission performance is determined including an equivalent circuit to numerically predict the lower cutoff frequency. A near field electromagnetic interference measurement is carried out compared to a reference board to investigate the simultaneous switching noise suppression ability.

Effect of surface finishing on signal transmission loss of microstrip copper lines for high-speed PCB

Microstrip copper lines play an important role in high-speed printed circuit boards. It is necessary to perform appropriate surface finishing on the microstrip copper lines to avoid oxidation and reduce the loss of signal transmission. In this work, the microstrip copper lines after micro etching treatment were finished with immersion silver, immersion tin and electroless nickel immersion gold (ENIG), respectively. Surface microstructures, 3D features and surface contact angle were examined to find the effect of the copper finishing on signal transmission loss. The results indicated that the microstrip copper lines with micro-etching treatment exhibits low signal transmission loss as − 39.9 dB/m at 20 GHz. The tested microstrip copper lines showed that signal transmission loss follows an increasing trend successively with micro etching treatment, immersion silver treatment, immersion tin treatment and ENIG treatment.

Techniques of impedance matching for minimal PCB channel loss at 40 GBPS signal transmission

PurposeThis paper aims to analyze the negative impact of surface mount (SMT) pad and imperfect via structure such as stub, pad, non-functional pad (NFP) and anti-pad on the signal integrity at 40 Gbps transmission on printed circuit board (PCB) due to impedance mismatch or discontinuity. The optimized modeling of via and SMT structures is performed to achieve minimal impedance mismatch and insertion loss less than 10 dB for six-inch full path transmission line between transmitter and receiver on PCB at Nyquist frequency 20 GHz.Design/methodology/approachThis work is split into two phases. The first phase involves optimization of via and SMT structures in three-dimensional electromagnetic (3DEM) simulation using Hyperlynx Via Wizard and Keysight EMPro software, respectively, followed by analysis of time domain reflectometry (TDR) and insertion loss (Sdd21). Whereas, in the second phase, full path hybrid mode simulation involving vias for signal layer transition, a 6-inch PCB channel and SMT pads is performed using Keysight ADS software to observe the TDR, Sdd21 and eye diagram at 40 Gbps transmission.FindingsImperfect via and SMT structures have a negative effect on signal reflection and attenuation. The optimized via and SMT minimizes the impedance mismatch by 81 per cent and insertion loss by 4.5 dB, ultimately enlarging the eye diagram opening to achieve minimal data loss at receiver with 40 Gbps transmission.Originality/valueThe results of original empirical research work on signal integrity analysis that optimizes the PCB channel design to achieve 40 Gbps signal transmission are presented in this study. It serves as a reference guide for high-speed PCB layout design.

Analytical Modeling of Metamaterial Differential Transmission Line Using Corrugated Ground Planes in High-Speed Printed Circuit Boards

An analytical model for metamaterial differential transmission lines (MTM-DTLs) with a corrugated ground-plane electromagnetic bandgap (CGP-EBG) structure in high-speed printed circuit boards is proposed. The proposed model aims to efficiently and accurately predict the suppression of common-mode noise and differential signal transmission characteristics. Analytical expressions for the four-port impedance matrix of the CGP-EBG MTM-DTL are derived using coupled-line theory and a segmentation method. Converting the impedance matrix into mixed-mode scattering parameters enables obtaining common-mode noise suppression and differential signal transmission characteristics. The comprehensive evaluations of the CGP-EBG MTM-DTL using the proposed analytical model are also reported, which is validated by comparing mixed-mode scattering parameters Scc21 and Sdd21 with those obtained from full-wave simulations and measurements. The proposed analytical model provides a drastic reduction of computation time and accurate results compared to full-wave simulation.

Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs

It is necessary for cost consideration to minimize the number of the used layers in a high-speed printed circuit board (PCB) design. In this paper, any independent net cannot be treated as a bus-oriented net in a high-speed PCB design because of no timing-matching constraint on an independent net. Any independent net in a high-speed PCB design can be modeled to obey the via-count constraint as the maximum number of the permitted vias for signal integrity. Clearly, the introduction of the permitted vias onto the independent nets can lead to the reduction on the number of the used layers in a high-speed PCB design. Given a set of bus-oriented nets and a set of independent nets with a via-count constraint in a high-speed PCB design, by introducing virtual vias onto independent nets and eliminating redundant vias on any used layer, a generalized algorithm can be proposed to minimize the number of the used layers with satisfying the via-count constraint on any independent net and assign the given bus-oriented nets and the separated segments inside the given independent nets onto the used layers. Compared with Yan’s algorithm with no via introduction on independent nets, the experimental results show that our proposed algorithm with ${c_{\max } = 1}$ , ${c_{\max } = 2}$ , ${c_{\max } = 3}$ , ${c_{\max } = 4}$ , and ${c_{\max } = 5}$ use reasonable CPU time to insert permitted vias to reduce 2.1, 2.8, 3.8, 4.4, and 4.6 used layers on the average for ten tested examples, respectively. Compared with a two-phase algorithm with via introduction on independent nets, the experimental results show that our proposed algorithm with ${c_{\max } = 1}$ , ${c_{\max } = 2}$ , ${c_{\max } = 3}$ , ${c_{\max } = 4}$ , and ${c_{\max } = 5}$ use less CPU time to reduce 1.6, 1.7, 1.7, 1.6, and 1.5 used layers on the average with increasing 13.3%, 16.3%, 10.6%, 4.2%, and 2.6% of the total used vias on the independent nets for ten tested examples, respectively.