Abstract
This brief describes a high-speed optoelectronic receiver implemented in 65 nm CMOS technology. The receiver utilizes only two clock phases instead of the four conventionally used in a quarter-rate clocking system. This two-clock phase system is enabled by a passive silicon photonic split and delay structure that eliminates the need for a quadrature clock phase generator and all the associated buffers. Moreover, the outputs of the receiver are demultiplexed which further helps reducing power consumption in the digital part of the system. The receiver also employs inter-stage AC coupling and is mounted on a high-speed printed circuit board (PCB). The impact of AC coupling and PCB parasitics is investigated. The functionality of the receiver is validated by high-speed optical measurements. The receiver achieves an error-free transmission (BER < 10−12) up to a data rate of 12.5 Gb/s with an energy efficiency of 1.93 pJ/bit and sensitivity of −4 dBm from a 1 V supply.
Highlights
O PTICAL interconnects offer an attractive alternative for copper high-speed interconnects that suffer from many limitations at high-speed
In these energy-efficient optical receivers, four or two clock phases are used for clocking the comparators and for demultiplexing the output at quarter or half the data rate
SYSTEM ARCHITECTURE The receiver is designed to take advantage of a validated silicon photonic (SiP) split-delay structure shown in Fig. 2 and detailed in [10]
Summary
O PTICAL interconnects offer an attractive alternative for copper high-speed interconnects that suffer from many limitations at high-speed. 30 to 45 % of a receiver power consumption is attributed to clock generation and/or clock buffering [7]–[9] In these energy-efficient optical receivers, four or two clock phases are used for clocking the comparators and for demultiplexing the output at quarter or half the data rate. Eliminating or reducing the clock buffering in these systems could result in overall more energy efficient solutions In this brief, a receiver is designed to exploit passive optical delay lines to eliminate the electronic clock generation and buffering circuits through the sampling scheme shown in Fig. 1 (b). A receiver is designed to exploit passive optical delay lines to eliminate the electronic clock generation and buffering circuits through the sampling scheme shown in Fig. 1 (b) This brief is organized as follows: Section II presents the overall architecture of the receiver and the circuit implementation.
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