High-speed Printed Circuit Board Design Research Articles

Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs

It is necessary for cost consideration to minimize the number of the used layers in a high-speed printed circuit board (PCB) design. In this paper, any independent net cannot be treated as a bus-oriented net in a high-speed PCB design because of no timing-matching constraint on an independent net. Any independent net in a high-speed PCB design can be modeled to obey the via-count constraint as the maximum number of the permitted vias for signal integrity. Clearly, the introduction of the permitted vias onto the independent nets can lead to the reduction on the number of the used layers in a high-speed PCB design. Given a set of bus-oriented nets and a set of independent nets with a via-count constraint in a high-speed PCB design, by introducing virtual vias onto independent nets and eliminating redundant vias on any used layer, a generalized algorithm can be proposed to minimize the number of the used layers with satisfying the via-count constraint on any independent net and assign the given bus-oriented nets and the separated segments inside the given independent nets onto the used layers. Compared with Yan’s algorithm with no via introduction on independent nets, the experimental results show that our proposed algorithm with ${c_{\max } = 1}$ , ${c_{\max } = 2}$ , ${c_{\max } = 3}$ , ${c_{\max } = 4}$ , and ${c_{\max } = 5}$ use reasonable CPU time to insert permitted vias to reduce 2.1, 2.8, 3.8, 4.4, and 4.6 used layers on the average for ten tested examples, respectively. Compared with a two-phase algorithm with via introduction on independent nets, the experimental results show that our proposed algorithm with ${c_{\max } = 1}$ , ${c_{\max } = 2}$ , ${c_{\max } = 3}$ , ${c_{\max } = 4}$ , and ${c_{\max } = 5}$ use less CPU time to reduce 1.6, 1.7, 1.7, 1.6, and 1.5 used layers on the average with increasing 13.3%, 16.3%, 10.6%, 4.2%, and 2.6% of the total used vias on the independent nets for ten tested examples, respectively.

Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs

It is known that bus-oriented escape routing and area routing are necessary in a high-speed printed circuit board (PCB) design. In this paper, given a set of global routed buses in a high-speed PCB design, it is assumed that the routed nets in a single bus are represented as a bus-oriented net between two escaped boundary pins. Based on the construction of a virtual wall between two circuit components, the connection transformation of the given bus-oriented nets inside a closed region and the construction of a covering graph for the represented intervals, an iterative modified left-edge algorithm is proposed to minimize the number of the assigned layers and assign all the bus-oriented nets onto the available layers. Compared with Tsai’s algorithm, the experimental results show that our proposed algorithm reduces 15.0% of the layer number and 21.9% of CPU time for six tested examples on the average, respectively. Compared with Chin’s algorithm, the experimental results show that our proposed algorithm use less CPU time to reduce 15.0% of the layer number for six tested examples on the average.

Revisiting the Effect of Nickel Characteristics on High-Speed Interconnect Performance

It has been observed that some surface finish like nickel–gold plating has exhibited significantly higher losses than expected on high-speed interconnects like printed circuit board (PCB) trace and packaging. The investigation has revealed that this extra loss results from the ferromagnetic characteristics of nickel material with large resistivity and nonunit frequency-dependent relative permeability. As a result, a high-speed PCB design must take into account the board surface finish effect, solder-mask coating, and the physical geometry deformation of copper related to the etching process when modeling the PCB trace, which can be accomplished by using 3-D electromagnetic field simulation tools. Simulation results are correlated with vector network analyzer (VNA) measurements on several test cases and also on the actual application boards. In our experimental studies on PCB test structures with electroless nickel/immersion-gold (ENIG) and electroplated nickel–gold plating, there is no observation of resonating anomalies in the insertion loss and group delay related to nickel permeability. Both simulation and measurement results have demonstrated that PCB board with ENIG and solder mask over bare copper finish has less signal loss than that with ENIG or hard-gold finish.

Signal integrity analysis of high speed and high density PCB design based on FPGA

According to the Moore's law,it becomes more and more complex to design high-speed and high-density Printed Circuit Board (PCB).As to Signal Integrity (SI) of large or extra large high-speed and high-density PCB,a research method combing theory analysis and mode simulation with project practice was introduced;meanwhile,some solutions or design rules were put forward.Following issues were discussed:PCB stack-up,the styles of transmission line,characteristic impedance calculation,topology,terminations,delay matching,crosstalk,differential pair layout,etc.On this basis,a few of principles were given about multilayers PCB design based on Field Programmable Gate Array (FPGA).Specific project application proves that high-speed and high-density PCB design can get good practical results driven by these principles or mechanisms.

A Theoretical Investigation of the Resonance Damping Performance of Magnetic Material Coating in Power/Ground Plane Structures

Power bus structure, consisting of two parallel solid power and ground planes separated by an insulator, behaves as a cavity resonator at high frequencies. Noise on the power bus, due to a sudden change in the current drawn by an active component, can appear as an undesired spatial fluctuation in the voltage between power and ground, especially at resonant frequencies of the resultant cavity, which may lead to problems in signal integrity, excessive delays, false switching, and radiated emission. These resonances can be suppressed by introducing high-frequency loss into the structure. This paper investigates a simple method to reduce self-/transfer impedance of power/ground planes for mitigating power/ground bounce in high-speed printed circuit board design by adding a thin layer of magnetic material coating to the inside-facing surfaces of copper power and ground plates to increase their effective high-frequency surface impedance. The increased surface impedance will increase the attenuation constant of the propagating wave inside the cavity that benefits reduction of cavity's quality factor (Q factor). The simulation results obtained from a modified cavity resonator model show that increasing surface impedance can dramatically reduce self- and transfer impedances at board resonant frequencies.

PCB Structure with a Guard Band for Suppressing Electromagnetic Radiation

Electromagnetic (EM) radiation from a feed cable attached to a printed circuit board (PCB), which is commonly encountered electromagnetic interference (EMI) problem at high-speed electronic PCB designs, is investigated by experimental and finite-difference time-domain (FDTD) modeling. In this paper, we propose and demonstrate a guard-band structure as a method for suppressing the EM radiation from a PCB with a feed cable. A signal trace is located between two ground traces (guard-band: GB). Four different cross-sectional PCB structures, which are commonly used in microwave integrated circuits as typical structures, are used to compare the guard-band structure. Frequency response of common-mode (CM) current, electric field near a PCB, and far electric field (radiated emission) are investigated as characteristics of the EMI. Results show that the shield structure is effective in suppressing the CM current at lower frequency. However, structures in which a conductive plate exists near the signal trace yield resonances with high level peak on CM current, near and far-field. On the other hand, the guard-band structure is more effective than other structures in suppressing the EM radiation in the considered frequency range. Therefore the guard-band will be effective for high-density PCB packaging with high-speed traces.

Practical issues in high speed PCB design

Current high-speed PCB (printed circuit board) designs need extra care due to the frequency of operation and reduced rise time signals. We present the main issues and parameters that a PCB designer has to consider and analyze before a board layout is created. First order approximation equations for various parameters are presented, based on the geometry of the PCB traces. Some useful design practices are also mentioned. As the speed of operation increases, the variables that are neglected in the lower frequency/higher rise time situation become more significant. Such parameters increase the complexity of the design. Three-dimensional analysis becomes a must to calculate and model interconnects accurately. This is where field solvers and the role of the signal integrity engineer come into play.

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).