High Speed Phase Frequency Detector Research Articles

A Low Power CMOS Phase Frequency Detector in High Frequency PLL System

The design of low power consumption for the different application and electronic product has become one of the challenges in high performance of Very Large Scale Integration (VLSI) design today. Therefore, many techniques have been introduced to minimize the power consumption and one of the technique is by using Multi-threshold Complementary Oxide Semiconductor (MTCMOS) power gating technique. This paper aimed to design a High Speed Phase Frequency Detector (HSPFD) using MTCMOS power gating technique implemented in 130 nm CMOS technology by using Cadence Virtuoso Tool. This design achieved a power consumption of 0.116 µW and frequency of 1.26 GHz. The result shows that the power consumption of HSPFD with MTCMOS power gating technique achieved about 67.14% smaller than conventional HSPFD while the frequency improved about 26%. The total area of the proposed HSPFD is 1423 µm2 (61.1100 µm x 23.290 µm). It can be conclude that, this design has better performance compared to previous work and it is suitable for applications like wireless communication system that need low power blocks to have long life battery.

Analysis and Reduction of Power in all Digital PLL Architecture by using Dynamic PFD with CWSP

Dynamic Phase Frequency Detector with CWSP, Mainly focusing on reducing power consumption, and fast-locking ability and has been used to reduce the delay moments Demonstrated 0.25μm CMOS technology. DTC needed assistance through a phase prediction means substantial energy savings and thus reduces range. A Low power all digital phase Locked Loop (PLL), they have become very attractive because good on a variety of actions, programmability, stability, portability, testability and yield and is better ADPLL Immunogenic noise. The key is to measure the time difference between time-to-digital converter Rising edges of signals. Time-to-digital converter (TDC) ADPLL integrated within. DTC delay Divided reference clock and the feedback clock is like the chain latch design is a comparison between the phase error Low power consumption. The complete ADPLL system improves the performance of the locking ability and the system DTC linearity. The design is implemented using DPFD with CWSP technique was more suitable for high speed phase frequency detector. The proposed system of dynamic phase frequency detector with CWSP has been fabricated and the corresponding power consumed is 75 μW.

A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre

A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.