High-speed Nonvolatile Memory Research Articles

A Three-Terminal Dual-Pillar STT-MRAM for High-Performance Robust Memory Applications

The design of a three-terminal self-aligned dual-pillar (DP) magnetic tunnel junction (MTJ) utilizing both current-induced spin-transfer torque (STT) and magnetic domain-wall motion effects is proposed for high-speed nonvolatile robust memory applications. The choice of a thin tunneling oxide (~0.9 nm) in a write-in port, spatially and electrically separated from a read-out port incorporating a thicker (~1.8 nm) oxide on an extended thin-film multilayer stack, significantly improves the overall cell stability and parametric process yield of a memory array. A dual-bit-line memory architecture incorporating a single-ended voltage-sensing scheme for fast data readout with just one access transistor per cell is also proposed for the first time. The technology-circuit cooptimization of the proposed single-transistor (1T) DP STT magnetic random access memory (MRAM) cell is carried out using effective mass-based transport simulations in nonequilibrium Green's function formalism and accurate micromagnetic simulations involving the Landau-Lifshitz-Gilbert-Slonczewski equation. The proposed DP STT-MRAM bit cell outperforms a state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell tunneling magnetoresistance, simplified memory array architecture with a single supply for read/write, and significantly lower probability of disturb and access failures under parametric process variations with a marginal increase in critical switching current.

Nonvolatile Memories with Dual-Layer Nanocrystalline ZnO Embedded Zr-Doped HfO[sub 2] High-k Dielectric

Metal-oxide-semiconductor memory capacitors composed of dual-layer nanocrystalline ZnO embedded zirconium-doped hafnium oxide high-k film were fabricated, characterized, and compared with those with the single-layer nanocrystalline ZnO embedded sample. Distinct layers of discretely dispersed nanocrystalline dots embedded in the amorphous high-k matrix were observed. The nanocrystalline ZnO dots trap many electrons. The dual-layer sample not only drastically increases the charge storage density but also improves the charge trapping speed due to the coulomb blockade effect. This is a potentially important gate dielectric structure for high density, high speed nonvolatile memories.

A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

New investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.

Partially Depleted SONOS FinFET for Unified RAM (URAM)—Unified Function for High-Speed 1T DRAM and Nonvolatile Memory

Unified random access memory (URAM) is demonstrated for the first time. The novel partially depleted (PD) SONOS FinFET provides unified function of a high-speed capacitorless 1T DRAM and a nonvolatile memory (NVM). The combination of an oxide/nitride/oxide (O/N/O) layer and a floating-body facilitates URAM operation in PD SONOS FinFETs. An NVM function is achieved by FN tunneling into the O/N/O stack and, a 1T-DRAM function is achieved by excessive-hole accumulation in the PD body. The fabricated PD SONOS FinFET shows retention time exceeding 10 years for NVM operation and program/erase time below 6 ns for 1T-DRAM in a single-cell transistor. These two memory functions are guaranteed without disturbance between them.

Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which is fabricated by using a top-down process technology. The NW cell exhibits faster program and erase (P/E) speed compared to the corresponding planar device; 1 mus for programming and 1 ms for erasing at VGS = plusmn11 V with a threshold voltage shift DeltaVTH of 2.6 V using the Fowler-Nordheim tunneling mechanism. At these P/E conditions, the planar device does not show appreciable change. The improvement is originated from: 1) increased electric field at the Si-SiO2 interface; 2) reduced effective tunnel barrier width; and 3) low electric field in the blocking oxide, as analyzed through simulation. In addition, good data retention makes the NW-based SONOS cell a potential candidate for future high-speed low-voltage NAND-type nonvolatile Flash memory applications.

PERFORMANCE MEASUREMENT OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE DESIGN

ABSTRACT Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

DESIGN OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE

ABSTRACT Increasing the memory density and utilizing the novel characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatile Memories

AbstractThe polarity of gates and the threshold voltages are primary parameters that determine the electric fields in the gate stack region of non-volatile memories. This field is central to programming, retention and the other characteristics of the devices. We have investigated the effect of the gate polysilicon polarity, experimentally, for silicon-oxide-nitride-oxide-silicon (SONOS) memory devices on silicon-on-insulator (SOI) wafers. An ultra-thin oxide-nitride-oxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention in our structures. The effect of ONO film, grown and deposited and of doping was simulated and characterized. Retention is affected by the electric field between the control gate and the storage node. Our experiments and simulations verify the consequences of different polarity of control gates through the change in electric field that they cause in retention and erase times for n+ and p+ polysilicon gate SONOS memories is verified through the characteristic energies of the processes.

Reproducible Resistance Switching in Ni/NiO/Ni Trilayer

AbstractThe resistance random access memory is attracting much attention as a high-density and high-speed non-volatile memory, having large resistance switching ration and good affinity with the conventional CMOS technologies. We demonstrate the resistance switching in the NiO thin film without using Pt electrode.

Comprehensive study on a novel bidirectional tunneling program/erase NOR-type (BiNOR) 3-D flash memory cell

In this paper a recently proposed bidirectional tunneling program/erase (P/E) NOR-type (BiNOR) flash memory is extensively investigated. With the designated localized p-well structure, uniform Fowler-Nordheim (FN) tunneling is first fulfilled for both program and erase operations in NOR-type array architecture to facilitate low power applications. The BiNOR flash memory guarantees excellent tunnel oxide reliability and is provided with fast random access capability. Furthermore, a three-dimensional (3D) current path in addition to the conventional two-dimensional (2D) conduction is proven to improve the read performance. The BiNOR flash memory is thus promising for low-power, high-speed, and high-reliability nonvolatile memory applications.

XTEM Study of the Microstructure of PZT Thin Films

Abstract Lead zirconate titanate (PbZrxTil-xO3, PZT) is one of the important ferroelectric materials for the storage elements of high-speed non-volatile memories. It also has much potential to be used in pyroelectric sensor, ultrasonic motor, and multiplayer ceramic capacitor. PZT (Zr/Ti = 48/52) thin films were prepared using a metal-organic decomposition (MOD) process. The precursor solution used for PZT thin film preparation was based on lead acetate trihydrate, Pb(CH3COO)2; zirconium nitrate, Zr(NO3)4.5H2O; and titanium nbutoxide, Ti(nC2H9)4. 2-butoxyethanol was chosen as a solvent. A 30% excess Pb was added to the precursor to compensate for the loss of lead oxide during the annealing process. Acetic acid was used as a complexing agent for PZT solution to control the hydrolysis and condensation rates. The 0.3M precursor solution was spin-coated on the Pt(111)/Ti/SiO2/Si substrates for 20s at 3000 rpm. The deposited film was fired at 450 °C for 10 min and repeated five times to burn out the organics. The films were crystallized at 600 °C in air for 1 hr.

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory

A charge-share modified (CSM) precharge-level architecture for selective subdataline activation designed to simultaneously achieve high-speed and low-power ferroelectric nonvolatile memories is described. In this architecture, to read the data of only one memory cell destructively, the precharge level of the selected subdataline is modified by charge-sharing between the subdataline and main dataline. This architecture enables high-speed read operations, because the operations of modifying the precharge level and reading the data of memory cells are achieved simultaneously. Three circuit technologies are used in the CSM architecture to increase the operating margin: self-timing precharge circuits which solve the polarization disturbance problem without adding extra signal lines or timing margins, a boosted precharge level technique which increases the signal voltage of the nonvolatile data, and shared dummy cell circuits which improve the precision of the reference voltage over that of a conventional voltage generator. These techniques and circuits are evaluated for a simulated 16-Mb ferroelectric memory. They reduce the access time by 20 ns to 51 ns compared with the conventional architecture, while reducing the memory array current to less than 1% that of the all-subdataline activation technology.

Application of the ferroelectric materials to ULSI memories

Memory is essential to electronic data processing and continuous efforts are being made to develop improved memory devices. In the era of VLSI, difficulties have arisen with respect to storage capacitance, which must be kept to a certain value while the device dimensions are reduced. This has prompted the adoption of complicated structures like the trench or stack, causing the number of process steps to be increased. The use of high dielectric constant materials has been researched for the extension of DRAM development. Recently, the development of the memories which use the polarization reversal current of the ferroelectric material is rapidly progressing because it enables high speed nonvolatile memory action which generally needed in recent electronic systems. These memories will replace a large portion of the existing memory systems in the near future. However, this is not a perfect solution to the problem, because they are not in accordance with the scaling rule. In this paper, it is shown that ferroelectric memories using the field effect current of a semiconductor by the remanent polarization of the ferroelectric material are in accordance with the scaling rule. The first experimental verification of the non-volatile memory action was reported by Moll and Tarui in 1963 [1]. This basic memory action has been successively used in MFS (metal-ferroelectric-semiconductor) transistors. The ferroelectric memories are nonvolatile and are expected to be high-speed devices, making them suitable for universal applications. However, it is necessary to optimize the interface between the semiconductor and ferroelectric material. Experiments for the prospective devices using CeO 2 or Ce x Zr (1− x) O 2 as the buffer insulator layers of the MFIS (metal-ferroelectric-insulator-semiconductor) transistors are described.