High-speed Network Systems Research Articles

Efficient connected-index finite-length arithmetic codes

In this paper, we propose a connected-index approach to construct efficient finite-length arithmetic codes by splitting the information of the last nonfitting symbol into the current and subsequent codewords. The proposed arithmetic codes, which limit the error propagation in about one block, require neither a post-appended end-of-block symbol, nor pre-affixed side-information, to characterize the number of encoded symbols. Hence, the proposed finite-length arithmetic codes can nearly achieve the coding efficiency attained by infinite-length arithmetic codes. With high coding efficiency, limited error-propagation, and the regular process, the proposed coding approach is suitable for information exchange with small packets in modern high-speed network systems.

A compact optical active connector: an optical interconnect module with an electrical connector interface

This paper describes a compact optical active connector that has both optical and electrical interfaces for an asynchronous-transfer-mode (ATM) switching system and high-speed computer network systems. This connector with an O/E or E/O conversion module can replace the conventional electrical-cable six-pin connector for an ordinary printed circuit board that has only an electrical interface. Our connector consists of a specially developed duplex MU-type submodule with photonic devices, an electrical connector, and integrated circuits (ICs). It can be used for 620-Mbps data transmission and has lower electromagnetic radiation noise than conventional connectors. Using optical active connectors to replace electrical-cable connectors will facilitate the introduction of high-throughput, large-capacity ATM switching systems, and next-generation local area network systems.

UTLB

An important aspect of a high-speed network system is the ability to transfer data directly between the network interface and application buffers. Such a direct data path requires the network interface to "know" the virtual-to-physical address translation of a user buffer, i.e ., the physical memory location of the buffer. This paper presents an efficient address translation architecture, User-managed TLB (UTLB), which eliminates system calls and device interrupts from the common communication path. UTLB also supports application-specific policies to pin and unpin application memory. We report micro-benchmark results for an implementation on Myrinet PC clusters. A trace-driven analysis is used to compare the UTLB approach with the interrupt-based approach. It is also used to study the effects of UTLB cache size, associativity, and prefetching. Our results show that the UTLB approach delivers robust performance with relatively small translation cache sizes.

UTLB

An important aspect of a high-speed network system is the ability to transfer data directly between the network interface and application buffers. Such a direct data path requires the network interface to "know" the virtual-to-physical address translation of a user buffer, i.e ., the physical memory location of the buffer. This paper presents an efficient address translation architecture, User-managed TLB (UTLB), which eliminates system calls and device interrupts from the common communication path. UTLB also supports application-specific policies to pin and unpin application memory. We report micro-benchmark results for an implementation on Myrinet PC clusters. A trace-driven analysis is used to compare the UTLB approach with the interrupt-based approach. It is also used to study the effects of UTLB cache size, associativity, and prefetching. Our results show that the UTLB approach delivers robust performance with relatively small translation cache sizes.

High-throughput data compressor designs using content addressable memory

The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well known LZ77 algorithm. The architecture mainly consists of three units, namely, content addressable memory, match-logic unit, and output-stage unit. The content-address-memory unit generates a set of hits signals which identify those positions whose symbols in a specified window are the same as the input symbol. These hits signals are then passed to the match-logic unit which determines both match length and location to form the kernel of compressed data. These two items are then passed to the output-stage unit for packetisation before being sent out. Simulation results show that, based on a 0.8 µm CMOS process technology, a clock speed of up to 50 MHz can be achieved for a VLSI design containing a 2 K buffer size. This implies that the developing data compressor chip can handle many real-life applications, such as in high-speed data storage and networking systems.

High-performance I/O for massively parallel computers: problems and prospects

Over the past two decades (1974-94), advances in semiconductor and integrated circuit technology have fuelled the drive toward faster, ever more efficient computational machines. Today, the most powerful supercomputers can perform computation at billions of floating-point operations per second (gigaflops). This increase in capability is intensifying the demand for even more powerful machines. Computational limits for the largest supercomputers are expected to exceed the teraflops barrier in the coming years. Discussion is given on the following areas: the nature of I/O in massive parallel processing; operating and file systems; runtime system and compilers; and networking technology. The recurrent themes in the parallel I/O problem are the existence of a great variety in access patterns and the sensitivity of current I/O systems to these access patterns. An increase in the variability of access patterns is also expected, and single resource-management approaches will likely not suffice. Providing the I/O infrastructure that will support these requirements will necessitate research in operating systems (parallel file systems, runtime systems, and drivers), language interfaces to high-performance storage systems, high-speed networking, graphics and visualization systems, and new hardware technology for I/O and storage systems. >

An approach to realizing interoperability using APPC

With the advent of reliable and high-speed network systems and intelligent database management systems, distributed systems are no longer a myth. There is a rapid development of software as well as hardware technology to support the distributed environment. Many researchers have done work in this field and several technical papers can be found cited in various textbooks 1–6. More and more, the need to realize open systems is becoming inevitable. Interoperability is no more just an idea but a reality. At the same time, more systems are looking for protocols to support dialog paradigm. This paper describes a conceptual framework for an architecture using the Advanced Program-to-Program Communications LU 6.2 protocol for illustrative purposes to achieve interoperability.