High-speed Logic Circuits Research Articles

Formation CMOS Schemes on GaAs with Self-Aligned Nitride and Silicide Gates

Advanced integrated logic circuits on GaAs are mainly based on the using of n-channel field-effect transistors with gate Schottky (MESFET). To create the complementary MESFET integrated circuits the main problem is quite small Schottky barrier height (< 0,5 eV) on p-type gallium arsenide. One way to solve this problem is to use a nitride or silicide tungsten compounds to form gates given the thickness and composition.
 This paper highlights the features of the formation of complementary high-speed logic circuits on the p-GaAs with self-aligned gate based on nitride or silicide of tungsten obtained by reduced pressure horizontal reactor "Izotron 4" and of RF magnetron sputtering equipment "Oratorio-5." This technology can also be used to form a Schottky contact to n- channel MESFET.
 Since the manufacturing process of MESFET self-aligned gate provides using refractory gate material as a mask for the multiply ion implantation, the Schottky contact must withstand subsequent high-temperature heat treatment required to activate implanted impurities. In this connection, the action of high-temperature photonic and resistive heating on the barrier height of Schottky contact formed by nitride (silicide) tungsten (WNx, WSix) GaAs was also studied.

MoS2 transistors operating at gigahertz frequencies.

The presence of a direct band gap and an ultrathin form factor has caused a considerable interest in two-dimensional (2D) semiconductors from the transition metal dichalcogenides (TMD) family with molybdenum disulfide (MoS2) being the most studied representative of this family of materials. While diverse electronic elements, logic circuits, and optoelectronic devices have been demonstrated using ultrathin MoS2, very little is known about their performance at high frequencies where commercial devices are expected to function. Here, we report on top-gated MoS2 transistors operating in the gigahertz range of frequencies. Our devices show cutoff frequencies reaching 6 GHz. The presence of a band gap also gives rise to current saturation, allowing power and voltage gain, all in the gigahertz range. This shows that MoS2 could be an interesting material for realizing high-speed amplifiers and logic circuits with device scaling expected to result in further improvement of performance. Our work represents the first step in the realization of high-frequency analog and digital circuits based on 2D semiconductors.

Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

Domino Logic Topologies of OR Gate with Variable Threshold Voltage Keeper

In this paper, we tend to take four domino circuit topologies to boost the strength and lower the consumption of power. A high speed and noise immune domino logic circuit is given that uses the property of the footer semiconductor to raise the sensitivity of the dynamic node to noise and eventually in improved performance. Dynamic logic circuits are used for prime performance and high speed applications. We tend to analyze and compare completely different domino logic style topologies for lowering the sub-threshold outpouring current in standby mode NMOS block , increasing the speed and increasing the noise immunity. We tend to compare power, delay, and Power Delay Product (PDP) of various topologies. Simulation is finished employing a 45nm cadence tool for eight input OR circuit. Our projected circuits scale back power consumption by 100 percent to 35 the troubles, improvement of unity noise gain of 39% to 85% and have a higher figure of advantage as compared to conditional keeper domino. The simulation results unconcealed that prime Speed Conditional keeper Domino (CKD) circuit offers the most effective ends up in terms of reduction in delay and power consumption as compared to different circuits.

Performance Investigation of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET for Low Volatge Digital Applications

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

A Current-Density Centric Logical Effort Delay and Power Model for High-Speed CML Gates

This paper presents a logical effort delay and power model for high-speed current-mode logic (CML) circuits. Current density centric and voltage swing dependent logical effort parameters are defined in terms of the characteristic current density for peak transistor cutoff frequency, which remains relatively constant across different technology nodes. Based on this model, constant and non-constant current density biasing schemes in data-paths of CML circuits are investigated and optimized for delay, power, and energy-delay metrics. The proposed model is simple yet sufficiently accurate for technology nodes in the constant-field scaling regime.

Emitter-coupled spin-transistor logic

The recent invention of magnetoresistive bipolar spin-transistors makes possible the creation of new spintronic logic families. Here we propose the first logic family exploiting these devices, extending emitter-coupled logic (ECL) to achieve a greater range of basis logic functions. By placing the wire from the output stage of ECL logic elements near spin-transistors in other logic stages throughout the circuit, additional basis logic elements can be realized. These new logic elements support greater logic minimization, resulting in enhanced speed, area, and power characteristics. A novel magnetic shielding structure provides this logic family with the crucial ability to cascade logic stages. This logic family potentially achieves a power-delay product 10–25 times smaller than conventional ECL, and can therefore be exploited to increase the performance of very high-speed logic circuits while broadening the range of design choices for a variety of electronic applications.

Single Exciton Quantum Logic Circuits

We describe new logic devices based on the storage and shuttling of individual excitons, called the single exciton quantum (SEQ) logic. SEQ logic can implement memory, concatenation, fan-out, and gain. The logic circuits are based on quasi 1-D semiconductors that are coupled to quantum dots (QDs) and on the engineering of their respective exciton states. The coding of binary states is based on the presence or absence of excitons in the QD, and the 1-D semiconductors serve as interconnects for shuttling excitons from one QD to another. Here, the QD serves as memory where the storage of excitonic excitations can be controlled electrically. Their transfer between 1-D semiconductors and QDs occurs through efficient nonradiative resonant energy transfer mechanisms. To allow low-power operations, the excitonic energy levels are cascaded to allow funneling of excitons where in the transfer of information is set to flow naturally in the direction of lower energy states. The principle of energy funnel, coupled with high drift velocity of excitons expected in 1-D semiconductors, allows low power, high speed logic circuits that can operate at room temperature. The use of excitons as a state-variable lends naturally to implementing optical interconnects for the input and output of an all-excitonic chip. Here, we describe the fundamental principles behind the proposed SEQ logic circuits, and describe the implementation of a universal nand logic.

40-Gb/s all-optical digital 4-bit priority encoder employing cross-gain modulation in semiconductor optical amplifiers

High-speed all-optical logic circuits have attracted much attention because of their important roles in signal processing in next-generation optical networks. The digital encoder is widely used in binary calculation, multiplexing, demultiplexing, address recognition and data encryption. A priority encoder allows the existence of multiple valid inputs simultaneously, identifies the priority of the request signals and encodes the priority. We propose and experimentally demonstrate an all-optical 4-bit priority encoder for return-to-zero signals at 40 Gbit/s based on cross-gain modulation in semiconductor optical amplifiers. Detuning filters after semiconductor optical amplifiers are employed to improve the output performance. Correct logic bit sequences and clear open eye patterns with extinction ratios exceeding 10 dB are achieved.

Short-channel and high-mobility p- and n-type organic single-crystal transistors with air-gap structures

ABSTRACTIn an effort to realize high-speed organic logic components, p- and n-type single-crystal organic field-effect transistors (SC-OFETs) were fabricated using air-gap structures with channel lengths as short as several μm. High carrier mobility of about 10 cm2/Vs is demonstrated in rubrene SC-OFETs even with the short channel length of 6 μm, using Si-based microstructures. The contact resistance is estimated to be 450 Ohm cm, which is only 5% of the total channel resistance between source and drain electrodes. Performances of n-type air-gap devices based on PDIF-CN2 are also demonstrated exhibiting electron transport with the carrier mobility of about 2 cm2/Vs. Furthermore, micron-scale air-gap structures are fabricated using insulating materials on glass substrates to reduce parasitic gate capacitance. The cut-off frequency of this rubrene air-gap device is measured to be as high as 8 MHz with applied drain voltage VD of 15 V. These techniques are promising to be applicable to next-generation organic high-speed logic circuits.

Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

It has been predicted that upsets due to Single-Event Transients (SETs) in logic circuits will increase significantly with higher operating frequency and technology scaling. For synchronous circuits manufactured at advanced technology nodes, errors due to single-event transients are expected to exceed those due to latch upsets. Experimental results presented in this paper quantify the contribution of logic errors to the total Soft-Error Rate (SER) for test circuits fabricated in a 40 nm bulk CMOS technology. These results can be used to develop guidelines to assist circuit designers adopt effective hardening strategies to reduce the SER, while meeting performance specifications for high speed logic circuits.

Current-density centric logical effort delay model for high-speed current-mode logic circuits

A simple yet accurate delay model based on the method of logical effort is presented for the analysis of high-speed current-mode logic (CML) circuits. The model describes the logical effort of a CML gate in terms of its operating current density normalised to the characteristic current density that yields peak transistor cutoff frequency (fT). Since the latter remains largely invariant over technology nodes as a result of constant-field scaling, the proposed logical effort model quantifies the effect of gate sizing, biasing and loading to simplify delay analysis for CML gates.

Bringing Superconductor Digital Technology to the Market Place

The unique properties of superconductivity can be exploited to provide the ultimate in electronic technology for systems such as ultra-precise analogue-to-digital and digital-to-analogue converters, precise DC and AC voltage standards, ultra high speed logic circuits and systems (both digital and hybrid analogue-digital systems), and very high throughput network routers and supercomputers which would have superior electrical performance at lower overall electrical power consumption compared to systems with comparable performance which are fabricated using conventional room temperature technologies. This potential for high performance electronics with reduced power consumption would have a positive impact on slowing the increase in the demand for electrical utility power by the information technology community on the overall electrical power grid. However, before this technology can be successfully brought to the commercial market place, there must be an aggressive investment of resources and funding to develop the required infrastructure needed to yield these high performance superconductor systems, which will be reliable and available at low cost. The author proposes that it will require a concerted effort by the superconductor and cryogenic communities to bring this technology to the commercial market place or make it available for widespread use in scientific instrumentation.

SEU Error Signature Analysis of Gbit/s SiGe Logic Circuits Using a Pulsed Laser Microprobe

We present, for the first time, an analysis of the error signatures captured during pulsed laser microprobe testing of high-speed digital SiGe logic circuits. 127-bit shift registers, configured using various circuit level latch hardening schemes and incorporated into the circuit for radiation effects self test serve as the primary test vehicle. Our results indicate significant variations in the observed upset rate as a function of strike location and latch architecture. Error information gathered on the sensitive transistor nodes within the latches and characteristic upset durations agree well with recently reported heavy-ion microprobe data. These results support the growing credibility in using pulsed laser testing as a lower-cost alternative to heavy-ion microprobe analysis of sensitive device and circuit nodes, as well as demonstrate the efficiency of the autonomous detection and error approach for high speed bit-error rate testing. Implications for SEU hardening in SiGe are addressed and circuit-level and device-level Radiation Hardening By Design recommendations are made

Regrown-emitter InP heterojunction bisucpolar transistors

We present the molecular beam epidaxy (MBE) growth and the dc device performance of the first fully epitaxial regrown-emitter InP heterojunction bipolar transistors (HBTs). Here the emitter layers are regrown by MBE onto a patterned base–collector template. This process is aimed at reducing the emitter resistance, a key parameter for scaling high speed logic circuits. Emitter resistance is reduced because the emitter contact is formed to an extrinsic emitter larger than the base–emitter junction. Scanning electron microscope images demonstrate controlled, uniform etching to the intrinsic base layer, high-quality epitaxial MBE growth onto the patterned surface, and good sidewall coverage. HBTs with base-emitter junctions ranging from 48×48 to 2.5×2.5μm2 have maximum dc current gains between 5.0 and 7.5. Comparison to regular HBTs shows that the dc current gains are limited by excess base currents. Possible contributions to the excess base currents are discussed. Transmission line method measurements show t...

Optical clock repetition-rate multiplier for high-speed digital optical logic circuits

Repetition-rate multiplication has been shown by use of a fiber ring oscillator with a semiconductor optical amplifier as the gain medium and by use of fast saturation and recovery of the amplifier from an external optical pulse train. Repetition-frequency multiplication up to 6 times and up to 34.68-GHz frequency have been achieved.

High-speed operation of static binary frequency divider using resonant tunnelling diodes and HEMTs

A new circuit technology using resonant tunnelling diodes and HEMTs makes the toggle frequency f/sub toggle/ of a static binary frequency divider close to the cutoff frequency f/sub t/ of the used 0.7 /spl mu/m-gate HEMTs. f/sub toggle/ and f/sub t/ are 34 and 38 GHz, respectively. This technology is promising for use in high-speed logic circuits.

Abrupt negative differential resistance in ungated GaAs FET's

We report on an investigation of an abrupt negative differential resistance (NDR) observed in the I-V characteristics of ungated GaAs FET's with submicron gate recess trenches. The NDR is a sensitive function of drain voltage, and its magnitude on the current axis and position on the voltage axis are functions of gate recess depth. The effect is attributed to fast intervalley scattering because of a modified electric field as etching proceeds, and it is possible that it can be used to implement high-speed logic circuits.

3.3-V BiCMOS current-mode logic circuits for high-speed adders

New high-speed BiCMOS current mode logic (BCML) circuits for fast carry propagation and generation are described. These circuits are suitable for reduced supply voltage of 3.3-V. A 32-b BiCMOS carry select adder (CSA) is designed using 0.5-/spl mu/m BiCMOS technology. The BCML circuits are used for the correct carry path for high-speed operation while the rest of the adder is implemented in CMOS to achieve high density and low power dissipation. Simulation results show that the BiCMOS CSA outperforms emitter coupled logic (ECL) and CMOS adders.