High-speed Heterojunction Bipolar Transistors Research Articles

LO Chain (×12) Integrated 190-GHz Low-Power SiGe Receiver With 49-dB Conversion Gain and 171-mW DC Power Consumption

A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featuring high-speed heterojunction bipolar transistors (HBTs) with ( $f_{\text {T}}$ , $f_{\text {max}}$ ) = (300, 500) GHz is presented. The core part of the receiver consists of a low-noise amplifier (LNA), an active tunable fundamental mixer, an intermediate frequency (IF) buffer amplifier (BA), and an active inverse balun. A wideband, high conversion gain (CG) local oscillator (LO) chain is integrated to make the receiver suitable for applications requiring tunable LO, which contains a multiplier with a multiplication factor of 12 ( $\times 12$ ) and a driver amplifier. To exploit the best possible performance with ultralow dc power consumption ( $P_{\text {dc}}$ ), the mixer and LNA transistors operate at forward-biased base–collector junction voltage ( $V_{\text {BC}}$ ). With a fixed IF frequency at 1 GHz, this receiver exhibits a peak CG of 49 dB with a 14-dB tuning range and a minimum single-sideband noise figure (NF) of 16.5 dB, consuming only 29-mW static dc power for the core part and 171 mW overall, including the LO chain. Within the CG tuning range, this receiver achieves a 6-dB RF bandwidth (BW) from 25 to 32 GHz. Compared with previously reported receivers at similar frequencies, the highest CG and the lowest $P_{\text {dc}}$ with highly competitive performance in terms of BW, CG tuning range, 1-dB output compression point, and NF have been achieved.

Impact of Breakdown Voltage on Gamma Irradiation Effects in 0.13- $\mu \text{m}$ and 0.25- $\mu \text{m}$ SiGe HBTs

We have investigated the ionization damage by 60Co gamma irradiation in 0.13- and 0.25- $\mu \text{m}$ SiGe heterojunction bipolar transistors (HBTs). Both technologies feature high-speed HBTs (HS-HBTs) together with high-voltage HBTs (HV-HBTs). Base current degradation with increasing total irradiation dose is studied. An identical behavior of corresponding HS-HBT and HV-HBT is found for operation in forward mode probing the emitter–base junction. In reverse mode where the collector base junction is determining the base current degradation, HV devices exhibit larger degradation than their HS counterparts. The increased width of the collector–base space charge region in HV devices leads to enhanced interface recombination at the adjacent Si/oxide interfaces and stronger base current degradation. TCAD simulations of device degradation suggest a linear relationship between total irradiation dose and radiation-induced interface state density $N_{\mathrm{ it}}$ .

A Multiregion Approach to Modeling the Base-Collector Junction Capacitance

The junction capacitance of heterojunction bipolar transistors (HBTs) is commonly modeled based on the theory of the p-n-homojunction with constant doping levels, made more flexible by the introduction of adjustable model parameters. In III–V HBTs, however, the low-doped collector is often not uniform, but contains both material and doping steps used to suppress the collector current blocking and to improve the linearity. Under these circumstances, the classical formulation is not sufficient to model the capacitance. Similarly, the exponential spatial doping dependence in the collector of modern high-speed HBTs may require a more in-depth approach. In this brief, a smooth expression for modeling the junction capacitance of a multiregion layer stack is presented. The accuracy of the new model is demonstrated based on both simulated and measured data.

Metamorphosis of the transistor into a laser

Based on the invention and operation of the transistor, the alloy diode laser, the quantum-well diode laser and the high-speed heterojunction bipolar transistor (HBT), we have invented and realized now a transistor laser (TL). The transistor laser is a three-terminal technology providing coupling and the coherent light emission in the transistor. The quantum-well (QW) heterojunction bipolar transistor laser, inherently a fast switching device, operates by transporting a small minority base charge density over a nanoscale base thickness in picoseconds. The TL, owing to its fast recombination speed, its unique three-terminal configuration, and complementary nature of its optical and electrical collector output signals, enables resonance-free base current and collector voltage modulation. It is a compact source of electro-optical applications such as nonlinear signal mixing, frequency multiplication, negative feedback, and optoelectronics logic gates.

Minority electron mobilities in GaAs, In0.53Ga0.47As, and GaAs0.50Sb0.50 calculated within an ensemble Monte Carlo model

The minority electron transport is crucial for the performances of heterojunction bipolar transistors (HBTs). Among the III-V semiconductors family, GaAsSb exhibits several advantages making it a serious candidate for the new generation of high speed HBTs. However, this alloy suffers from a lack of experimental studies. Properties such as electronic structure and charge carrier mobilities are of prime importance in theoretical device operation calculations. In this article, we investigate the minority electron mobilities by means of an ensemble Monte Carlo modeling including polar optical phonon–plasmon coupling through a self-consistent dielectric function. Realistic electronic structures are provided by a nonlocal empirical pseudopotential method. It is found that GaAs0.50Sb0.50 does not show a mobility enhancement for very high acceptor doping levels unlike GaAs and Ga0.47In0.53As.

A 0.13 $\mu{\hbox {m}}$ SiGe BiCMOS Technology Featuring f$_{T} $/f$_{\max}$ of 240/330 GHz and Gate Delays Below 3 ps

A 0.13 μm SiGe BiCMOS technology for millimeter-wave applications is presented. This technology features high-speed HBTs with peak transit frequencies <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 240 GHz, maximum oscillation frequencies <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 330 GHz, and breakdown voltages BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> of 1.7 V along with high-voltage HBTs ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> = 50 GHz, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> = 130 GHz, BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> = 3.7 V) integrated in a dual gate oxide RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> oscillators with fundamental-mode oscillation frequencies above 200 GHz are demonstrated.

3D Wafer-Scale Integration for RF and Digital Applications

Northrop Grumman Space Technology has developed an integration technology that is capable of intimately integrating III-V semiconductor devices with Si CMOS under DARPA's COSMOS program. The integration approach is based on a direct face-to-face bonding between pre-fabricated III-V chiplets and CMOS wafers. It is capable of integrating CS (compound semiconductor) devices from smaller wafer substrates to a larger Si host wafer as well as integrating multiple CS technologies onto the same Si CMOS host wafer. This process can be applied to virtually any CS and Si technologies. Integrated differential amplifiers (DAs) have been demonstrated using this 3D AHI integration approach. This DA demonstration integrates the 0.18um Silicon CMOS technology with 6 layers of interconnections from Jazz Semiconductor and NGST's 0.4um emitter high speed HBT technology. Further integration details on AHI as well as demonstrated integrated circuit data will be presented in the full paper.

Impact of inside spacer process on fully self-aligned 250 GHz SiGe:C HBTs reliability performances: a-Si vs. nitride

A critical process aspect of the bipolar device is the oxide isolation between the emitter and the extrinsic base. Indeed, it is a well known fact that the emitter–base junction degradation is mainly due to interface states generation underneath oxide spacer. This study demonstrates the large impact of the inside spacer process in fully-self aligned high speed HBT on its reliability. Several types of electrical stress have been investigated and the stress-induced degradation compared for nitride and a-Si (amorphous silicon) spacers. Aging results coupled with noise measurements and TCAD simulations allowed to explain the different observed behaviors, finally concluding on the significantly higher reliability performances of devices processed with a-Si spacers.

A Generalized SiGe HBT Single-Event Effects Model for On-Orbit Event Rate Calculations

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This work draws on experimental and simulation results to derive a generalized SEU response model for bulk SiGe HBTs. The model was validated using published heavy ion and new proton data gathered from high-speed HBT digital logic integrated circuits fabricated in the IBM 5AM SiGe BiCMOS process. Calibrating to heavy ion data was sufficient to reproduce the proton data without further adjustment. The validated model is used to calculate upset event rates for low-earth and geosynchronous orbits under typical conditions. </para>

Determination of conduction band offsets in type-IIIn0.27Ga0.73Sb∕InxAl1−xAsySb1−yheterostructures grown by molecular beam epitaxy

Low-temperature photoluminescence (PL) has been performed on a set of specially designed ${\mathrm{In}}_{0.27}{\mathrm{Ga}}_{0.73}\mathrm{Sb}∕{\mathrm{In}}_{x}{\mathrm{Al}}_{1\ensuremath{-}x}{\mathrm{As}}_{y}{\mathrm{Sb}}_{1\ensuremath{-}y}$ multiple quantum well (MQW) heterostructures grown by molecular beam epitaxy in order to provide a measure of the conduction band offsets in this material system. These alloys are of interest for the development of high-speed heterojunction bipolar transistors (HBTs) that show promise for operation at lower power dissipation than in $\mathrm{GaAs}$- and $\mathrm{InP}$-based HBTs. Excitation power studies revealed evidence for strong electron-hole recombination at $0.56\phantom{\rule{0.3em}{0ex}}\mathrm{eV}$ within the $\mathrm{InGaSb}$ layers of the type-I MQW structure with $(x=0.52,y=0.25)$, while several weaker indirect transitions involving electrons in the ${\mathrm{In}}_{x}{\mathrm{Al}}_{1\ensuremath{-}x}{\mathrm{As}}_{y}{\mathrm{Sb}}_{1\ensuremath{-}y}$ and holes in the $\mathrm{InGaSb}$ layers were observed between 0.38 and $0.53\phantom{\rule{0.3em}{0ex}}\mathrm{eV}$ from the nominally type-II MQW samples with $(x,y)=(0.67,0.39)$ and (0.69,0.41). Neglecting small corrections $(\ensuremath{\sim}15\phantom{\rule{0.3em}{0ex}}\mathrm{meV})$ due to the electron and hole confinement energies, we estimate conduction band offsets of $\ensuremath{\sim}120--150\phantom{\rule{0.3em}{0ex}}\mathrm{meV}$ in these type-II structures. The general trends of the PL features as a function of excitation power have been reproduced from modeling of the quantum well electron and hole subband energies, including effects due to band bending at the heterointerfaces.

Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (SEB) and base gap resistance (RGAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced RGAP, from 16.48Ω to 4.62Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (CCB). Due to the reduced RGAP, the maximum oscillation frequency (fmax) for a 0.5μm-emitter HBT is improved from 205GHz to 295GHz, while the cutoff frequency (fT) is maintained at around 300GHz.

Thermal Resistance Characterization of Implanted Subcollector InP-Based HBTs

We present the results of measurements of thermal resistivity of the heterojunction bipolar transistor (HBT) devices, utilizing selective ion implantation to define the subcollector. This new device fabrication technique resulted in high-speed HBT devices with substantially reduced thermal resistivity, compared to devices utilizing the conventional fabrication approach which includes mesa isolation for pattern definition. The measurements were taken on full-thickness 3 InP wafers at T/sub amb/ from 30/spl deg/C to 180/spl deg/C and two separate emitter current densities. We present data on three device epitaxial structures with identical device layouts and discuss the relationship of V/sub be/ to temperature at these elevated power and temperature levels.

New collector undercut technique using a SiN sidewall for low base contact resistance in InP/InGaAs SHBTs

A new collector undercut process using SiN protection sidewall has been developed for high speed InP/InGaAs single heterojunction bipolar transistors (HBTs). The HBTs fabricated using the technique have a larger base contact area, resulting in a smaller DC current gain and smaller base contact resistance than HBTs fabricated using a conventional undercut process while maintaining low C/sub bc/. Due to the reduced base contact resistance, the maximum oscillation frequency (f/sub max/) has been enhanced from 162 GHz to 208 GHz. This result clearly shows the effectiveness of this technique for high-speed HBT process, especially for the HBTs with a thick collector layer, and narrow base metal width.

Applications and processing of SiGe and SiGe:C for high-speed HBT devices

The continued growth of high-speed-digital data transmission and wireless communications technology has motivated increased integration levels for ICs serving these markets. Further, the increasing use of portable wireless communications tools requiring long battery lifetimes necessitates low power consumption by the semiconductor devices within these tools. The SiGe and SiGe:C materials systems provide solutions to both of these market needs in that they are fully monolithically integratible with Si BiCMOS technology. Also, the use of SiGe or SiGe:C HBTs for the high-frequency bipolar elements in the BiCMOS circuits results in greatly decreased power consumption when compared to Si BJT devices. Either a DFT (graded Ge content across the base) or a true HBT (constant Ge content across the base) bipolar transistor can be fabricated using SiGe or SiGe:C. Historically, the graded profile has been favored in the industry since the average Ge content in the pseudomorphic base is less than that of a true HBT and, therefore, the DFT is tolerant of higher thermal budget processing after deposition of the base. The inclusion of small amounts of C (e.g. <0.5%) in SiGe is effective in suppressing the diffusion of B such that very narrow extremely heavily doped base regions can be built. Thus the f T and f max of a SiGe:C HBT/DFT are capable of being much higher than that of a SiGe HBT/DFT. The growth of the base region can be accomplished by either nonselective mixed deposition or by selective epitaxy. The nonselective process has the advantage of reduced complexity, higher deposition rate and, therefore, higher productivity than the selective epitaxy process. The selective epi process, however, requires fewer changes to an existing fabrication sequence in order to accommodate SiGe or SiGe:C HBT/DFT devices into the BiCMOS circuit.

Comparative study of electron transit times evaluated by DD, HD, and MC device simulation for a SiGe HBT

Transit times of a silicon/germanium heterojunction bipolar transistor (HBT) with a base width of 24 nm are investigated in the quasi-stationary limit for the first time by consistent drift-diffusion (DD), hydrodynamic (HD), and fullband Monte Carlo (MC) simulations. The quasi-ballistic transport in the base and collector leading to a strong velocity overshoot is well described by the HD model and corresponding transit times are in good agreement with the MC results. On the other hand, the DD model fails in this region and substantially overestimates the base transit time bearing the possibility of wrong guidelines for transistor design optimization. However, since the base transit time is no longer dominating the cutoff frequency of high-speed HBTs, the failure of the DD model leads to an underestimation of the peak cutoff frequency by only 10%. Close to high injection differences in the emitter transit times of the HD and MC model are observed which are mainly related to small differences in the Gummel plot.

InGaP/GaAs Sub-Square-Micron Emitter HBT with fmax > 100 GHz

InGaP/GaAs heterojunction bipolar transistors (HBTs) with a sub-square-micron emitter have been fabricated using a novel self-aligned emitter etching process with low damage and good lateral and vertical controllability. HBTs with an emitter size of 0.4×1.7 µ m fabricated using this process exhibited a current gain of 44 which is comparable to that of AlGaAs/GaAs HBTs. Furthermore, the HBTs exhibited excellent microwave performance. For an HBT with an emitter size of 0.4×2.2 µ m, a cutoff frequency (f T) of 55 GHz and a maximum oscillation frequency (f max) of 100 GHz were reached at a collector current (I C) as low as 1.0 mA, and a peak f T of 62 GHz and a peak f max of 105 GHz were obtained at I C=2.3 mA. As far as we know, this f max is the highest reported for GaAs-based HBTs with an emitter area of less than 1 µ m2. This process is thus promising for fabrication of high-speed HBT ICs with low power consumption.

The high-speed performance of [formula omitted] Schottky collector HBTs

We investigated the high-speed performance of Si 1−x Ge x/ CoSi 2 Schottky collector heterojunction bipolar transistors (SCHBTs). The fact that a Si/Si 1−x Ge x/ CoSi 2 SCHBT can suppress the base push out and eliminate the collector charging time, which is a delay component that makes a sizable contribution in high-speed heterojunction bipolar transistors (HBTs), makes it possible to obtain very high and current-stable speeds with this structure. Analysis of the different delay components contributing to the emitter-to-collector delay time shows that for Schottky collector transistors with a base thickness of 300 Å or less, the structure should be optimized to minimize the emitter delay time even at high collector current densities in order to further improve the speed. An advantage is the lower power consumption when this SCHBT is compared with conventional HBTs.

High-speed InP-InGaAs heterojunction phototransistors employing a nonalloyed electrode metal as a reflector

High-speed InP-InGaAs heterojunction phototransistors (HPT's) with a base terminal (three-terminal HPT's) have been fabricated. These HPT's have nonalloyed electrodes functioning as reflectors and a configuration in which light is incident through the substrate. These features lead to an increase in quantum efficiency in spite of the thin base and collector light-absorbing layers. Optical gain dependence on collector current is weak because of the low recombination current at the emitter-base interface. Maximum optical-gain cutoff frequencies of 22 and 14 GHz are obtained for a 3/spl times/3-/spl mu/m/sup 2/ emitter HPT illuminated by 1.3- and 1.55-/spl mu/m light, respectively. This HPT has the capability of operating as a high-speed heterojunction bipolar transistor (HBT) as well. A current-gain cutoff frequency (f/sub T/) of 128 GHz is obtained for a 3/spl times/9-/spl mu/m/sup 2/ emitter HBT fabricated on the same wafer. Equivalent circuit analysis, in which all the components are determined by measuring both the electrical and optical characteristics of a three-terminal HPT, shows good agreement with experimental results. >

Application of micro-airbridge isolation in high speed HBT fabrication

A new selfaligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) fabrication process is presented, featuring a deep wet etching that undercuts the base and the emitter interconnects, and forms micro-airbridges for device isolation. The advantages of this isolation process include critical lithographies on flat surfaces, capacitance reduction, and compatibility with thick collector layers. 1-5×10 μm 2 HBT devices, grown by MOCVD, exhibit an F max of 120 GHz

Behavior of Damage in Selectively Implanted SiGe/Si

AbstractEpitaxial SiGe/Si layers are being extensively investigated for use in base regions of high-speed heterojunction bipolar-transistors (HBTs). Extended defects can be formed in SiGe/Si layers by ion-implantation. Defects, once formed in the layers, can negatively impact electrical performance and also future reliability of the HBTs. The present study investigates the interaction between selective-implant damage and strained SiGe/Si layers of sub-critical thickness. Implant-damage is observed to form dislocation-sources at the edges of implanted regions in SiGe/Si heterolayers. The dislocation sources produce glide dislocation loops. Segments of these loops glide down to SiGe/Si interfaces causing misfit dislocations to arise at interfaces in the heterolayers. Misfitdislocations are formed in directions parallel to and perpendicular to the &lt;110&gt; edge of the implanted region. Dislocations propagate out to a distance of ∼100-150 nm past the edge of the implant in the case of Si0.9Ge0.1/Si layers of sub-critical thickness. The origin and behavior of these defects is discussed.