High Speed Flash ADC Research Articles

Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection

High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain equally spaced reference values. Because the proposed ADC utilizes offset voltages as references, no resistor ladder is required. We also developed a time-domain sorting mechanism for the offset voltages to achieve on-chip comparator selection. We first perform a detailed analysis of the order statistics based selection method and then design a 4-bit ADC in a commercial 65-nm process and perform transistor-level simulation. When using 127 comparators, INLs of 20 virtual chips are in the range of -0.34LSB/+0.29LSB to -0.83LSB/+0.74LSB, and DNLs are in the range of -0.33LSB/+0.24LSB to -0.77LSB/+1.18LSB at 1-GS/s operation. Our ADC achieves the SNDR of 20.9dB at Nyquist-frequency input and the power consumption of 0.84mW.

Front-end electronics for the FAZIA experiment

FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics.

English

As VLSI technology gaining more popular power consumption and high speed are the major constraints. In Mixed signal IC‟s it is a necessity of minimum power dissipation in order to limit energy in a reasonable size batteries. Analog to digital converter is the key to mixed signal IC‟s. Analog to digital converters are the basic component in modern communications, handheld wireless computers and signal processing systems. In this paper most preferred and high speed flash ADC using CMOS latch comparator is presented. Normally Flash Adc takes large number of comparators as size of ADC increases. In this comparator count will be decreased by using multiplexing of reference signal and reduce power dissipation using dynamic latch comparator. This design is simulated and results are presented. The presented flash ADC consumes 212.47uwatts power at a frequency of 1000 MHz with an operating voltage of 1.8v.

A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator

A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.

Design and Test of a High-Speed Flash ADC Mezzanine Card for High-Resolution and Timing Performance in Nuclear Structure Experiments

This work describes new electronics for the EXOGAM2 (HP-Ge detector array) and NEDA (BC501A-based neutron detector array). A new digitizing card with high resolution has been designed for gamma-ray and neutron spectroscopy experiments. The higher bandwidth requirement of the NEDA signals, together with the necessity for accuracy, require a high sampling rate in order to preserve the shape for real-time Pulse Shape Analysis (PSA).

New encoding scheme for high-speed flash ADC's

A new encoding scheme for high-speed flash analog to digital converters using a Wallace tree is described. It provides a global error filtering and its regular topology optimises the signal propagation. Its application to a 5-bit 1.4-GHz Gallium Arsenide analog-to-digital converter is described.

A 20 b dynamic-range floating-point data acquisition system

The design and engineering of a floating-point data-acquisition system are described. The system has both automatic gain and software-programmable gain adjustment features. In automatic gain adjustment mode, the gain is set automatically dependent on the input amplitude so that the full conversion resolution is maintained irrespective of the signal dynamic range. A high-speed flash ADC with an approximately 35 ns conversion time is used to convert the signal quickly into 8 b data. A programmable array logic (PAL) then transfers this 8 b digital data into 12 b information for setting the gain of the variable-gain amplifier. The amplifier gain settings are all powers of two; thus, the normalization of the digitized data requires only a bit shifting operation and no complex software division. The gain information and the 12 b sampling ADC output increase the dynamic range to 20 b. The software package includes commands needed for the system initiation, automatic gain or software programmable gain selection, sampling and conversion, and data normalization. >