High-speed Field Programmable Gate Array Research Articles

Accelerating electrostatic particle-in-cell simulation: A novel FPGA-based approach for efficient plasma investigations.

Particle-in-cell (PIC) simulation serves as a widely employed method for investigating plasma, a prevalent state of matter in the universe. This simulation approach is instrumental in exploring characteristics such as particle acceleration by turbulence and fluid, as well as delving into the properties of plasma at both the kinetic scale and macroscopic processes. However, the simulation itself imposes a significant computational burden. This research proposes a novel implementation approach to address the computationally intensive phase of the electrostatic PIC simulation, specifically the Particle-to-Interpolation phase. This is achieved by utilizing a high-speed Field Programmable Gate Array (FPGA) computation platform. The suggested approach incorporates various optimization techniques and diminishes memory access latency by leveraging the flexibility and performance attributes of the Intel FPGA device. The results obtained from our study highlight the effectiveness of the proposed design, showcasing the capability to execute hundreds of functional operations in each clock cycle. This stands in contrast to the limited operations performed in a general-purpose single-core computation platform (CPU). The suggested hardware approach is also scalable and can be deployed on more advanced FPGAs with higher capabilities, resulting in a significant improvement in performance.

Optimizing FPGA implementation of high-precision chaotic systems for improved performance.

Developing chaotic systems-on-a-chip is gaining much attention due to its great potential in securing communication, encrypting data, generating random numbers, and more. The digital implementation of chaotic systems strives to achieve high performance in terms of time, speed, complexity, and precision. In this paper, the focus is on developing high-speed Field Programmable Gate Array (FPGA) cores for chaotic systems, exemplified by the Lorenz system. The developed cores correspond to numerical integration techniques that can extend to the equations of the sixth order and at high precision. The investigation comprises a thorough analysis and evaluation of the developed cores according to the algorithm complexity and the achieved precision, hardware area, throughput, power consumption, and maximum operational frequency. Validations are done through simulations and careful comparisons with outstanding closely related work from the recent literature. The results affirm the successful creation of highly efficient sixth-order Lorenz discretizations, achieving a high throughput of 3.39 Gbps with a precision of 16 bits. Additionally, an outstanding throughput of 21.17 Gbps was achieved for the first-order implementation coupled with a high precision of 64 bits. These outcomes set our work as a benchmark for high-performance characteristics, surpassing similar investigations reported in the literature.

Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers

The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.

Control of the Probe-Sample Interaction Force at the Piconewton Scale by a Magnetic Microprobe in Aqueous Solutions

This article describes the design and implementation of a control system that controls the probe-sample interaction force at the piconewton scale by manipulating a magnetic microprobe in aqueous solutions under a microscope. The control system has two functions, namely accurate force generation by magnetic flux control and precise control of the probe-sample interaction force. Magnetic flux control uses an improved six-input-six-output digital control law along with a disturbance estimator to achieve two control objectives. First, the magnetic flux at each pole tip of a previously developed hexapole electromagnetic actuator can be individually and precisely controlled at frequencies over 4 kHz, and the experimental results precisely followed the theoretical predictions based on the design. Second, together with the optimized flux allocation, the flux control system generates precise magnetic forces, making the six-input hexapole actuator behave like a decoupled three-axis force generator with a bandwidth of more than 4 kHz. Interaction force control compares the measured deformation of the sample with the expected deformation, updated in real time by a deformation predictor, to generate the magnetic force to control the interaction between the probe and the sample. Digital control laws, the estimator, and the predictor are all implemented using a high-speed Field Programmable Gate Array (FPGA) system. Experiments confirm that through mathematical modeling, digital control technology, high-speed electronics, and real-time computation, accurate three-dimensional force generation at the piconewton scale with high bandwidth and precise interaction force control with zero-mean random error, attributed to random thermal force and measurement noise, are achieved.

A Tbit/s parallel real-time physical random number scheme based on chaos optical frequency comb of Si<sub>3</sub>N<sub>4</sub> micro-ring

<sec>Physical random numbers (PRNs) own various advantageous characteristics, including unpredictability, non-repeatability, higher security and reliability. Meanwhile, laser chaos has attracted great attention in the field of PRN. In terms of single channel PRN, laser chaos schemes can achieve a much higher bit-rate than traditional quantum PRN schemes. So far, various laser chaos PRN schemes have been discussed in order to enhance the performance of single channel laser chaos PRN. However, considering the limited bandwidth of laser chaos, especially the bandwidth of digital electronic circuit, the development potential of single channel PRN should be limited and may fall into the trap of high performance and expensive cost. Recently, the applications of multi-channel parallel PRN schemes have been developed. These parallel types may balance the high performance of PRN in a low cost. Recent progress indicates that chaotic micro-comb may have good potential. The micro-comb exhibits highly nonlinear and complex dynamic characteristics, and each comb tooth may show chaotic oscillation. The wavelength division multiplexing technology enables large-scale optical parallel output, providing the possiblity for large-scale parallel PRN generation. However, most of these PRN schemes are offline rather than true online and real-time random numbers. Thus, the development of real, online real-time parallel PRN solutions has great interest and research value in related fields.</sec><sec>Herein we experimentally demonstrat an ultra-high-speed parallel real-time physical random number generator, which is achieved though the combination of chaotic micro-comb of chip-scale Si<sub>3</sub>N<sub>4</sub> ultra-high Q micro-resonator and a high-speed field programmable gate array (FPGA). The results show that the Si<sub>3</sub>N<sub>4</sub> ultra-high Q micro-resonator generates a micro-comb with hundreds of channels, each channel can route into an optically chaotic state, and become an excellent physical entropy source. Using FPGA onboard multi-bit analog-to-digital converter, the filtered optical chaos signal from the micro-comb is discretely sampled and quantized, and resulting in an 8-bit binary bitstream. Taking real-time self-delayed exclusive or (XOR) processing of bitstream and preserving 4 least significant bits, the qualified physical random bitstream with real-time 5 Gbits/s rate is realized experimentally. Considering that there are 294 chaotic comb teeths, our approach anticipates a throughput of 1.74 Tbits/s of real-time physical random bits. Our results could offer a new integrated and ultra-high-speed option for real-time physical random number sources.</sec>

Design of A High-Precision Component-Type Vertical Pendulum Tiltmeter Based on FPGA.

This paper presents a high-precision component-type vertical pendulum tiltmeter based on an FPGA (Field Programmable Gate Array) that improves the utility and reliability of geophysical field tilt observation instruments. The system is designed for rapid deployment and offers flexible and efficient adaptability. It comprises a pendulum body, a triangular platform, a locking motor and sealing cover, a ratiometric measurement bridge, a high-speed ADC, and an FPGA embedded system. The pendulum body is a plumb-bob-type single-suspension wire vertical pendulum capable of measuring ground tilt in two orthogonal directions simultaneously. It is installed on a triangular platform, sealed as a whole, and equipped with a locking motor to withstand a free-fall impact of 2 m. The system utilizes a differential capacitance ratio bridge in the measurement circuit, replacing analog circuits with high-speed AD sampling and FPGA digital signal processing technology. This approach reduces hardware expenses and interferences from active devices. The system also features online compilation functionality for flexible measurement parameter settings, high reliability, ease of use, and rapid deployment without the need for professional technical personnel. The proposed tiltmeter holds significant importance for further research in geophysics.

Ultra-Precise High-Speed Untethered Manipulation of Magnetic Scanning Microprobe in Aqueous Solutions

This article describes the design and development of an integrated system that renders ultra-precise and high-speed, untethered manipulation of a single magnetic scanning microprobe in aqueous solutions under a microscope. The system uses a six-input-three-output hexapole electromagnetic actuator to control the magnetic gradient force exerted on the probe and a three-dimensional vision-based motion tracking system to enable feedback control. The control system has three core functions that enables superior manipulation of the magnetic microprobe. The six-input-six-output closed-loop magnetic flux control significantly suppresses the effect of magnetic hysteresis and greatly increases the bandwidth of magnetic flux generation. The optimal flux allocation solves four issues in multipole magnetic force generation: redundancy; coupling; nonlinearity; and position-dependency. The position-dependent discrete-time motion control law determines the required force for stabilization and tracking. These three core functions have been implemented using a high-speed field programmable gate array (FPGA) system. Experiments have verified that the use of digital control technology, high-speed electronics, mathematical modeling, and real-time computation has achieved superior manipulation of a single magnetic microprobe in aqueous solutions.

FPGA-Based Autonomous GPS-Disciplined Oscillatorsfor Wireless Sensor Network Nodes

Numerous devices in distributed wireless sensor arrays require a high-accuracy timing reference. Although the GPS-disciplined oscillators have been developed for decades, the hardware design still has performance limitations. In this context, we present the hardware implementation for a GPS-disciplined oscillator with an automatic adaptive drift correction algorithm, which is implemented in a low-cost, high-speed field-programmable gate array (FPGA) device. The system design and the hardware implementation are presented to demonstrate the advantages of the proposed oscillator. To verify this oscillator in real-time applications, we tested the device in multiple environments and compared it to state-of-the-art designs. The experimental results showed that our proposed device has a low cost and high performance. This device can achieve less than 80 ns and 356 ns in 1PPS signal drift in the indoor environment test and the outdoor environment test, respectively, after 24 h of working without a GPS signal.

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

FPGA implementation of epileptic seizure detection using semisupervised reduced deep convolutional neural network

In this article, an optimized variational mode decomposition (OVMD), reduced deep convolutional neural network (RDCNN), and multi-kernel random vector functional link network (MKRVFLN) are combined to recognize the epileptic seizure using electroencephalogram (EEG) signals. An improved particle swarm optimization based on the maximum value of log energy entropy is introduced to compute the optimized values of the number of band-limited intrinsic mode functions (BLIMFs) and the data-fidelity factor. The Kurtosis and correlation coefficient are used to extract the most efficient BLIMF from highly nonlinear and non-stationary multi-class epilepsy EEG signals. The RDCNN structure is designed to extract the most discriminative unsupervised features and feed into the novel supervised MKRVFLN classifier to train efficiently by reducing the cross-entropy loss for recognizing the seizure epochs efficaciously. The Bonn University, Germany, Neurology and Sleep centre, New Delhi single-channel EEG, and Boston Children’s Hospital multichannel scalp EEG (sEEG) datasets are considered to evaluate the overall efficiency of the proposed method. The proposed method has produced 100% classification accuracy (CA) for classification problem (CP) 1 to 4 present in database-A, as well as for all CP incorporated with database-B and also it has 99.88% CA for CP-5 of the Bonn University database using a ten-fold cross-validation strategy. Furthermore, the proposed method has also the sensitivity of 100%, specificity of 99.34%, and CA of 99.37% with a negligible false positive per hour (FPR/h) of 0.663% by adopting 50% training, 30% testing and 20% validation of total data present in Boston database and its overall performance outperforms as compared to other state-of-the-art methods. The less computational complexity, higher learning speed, accurate epileptic seizure recognition, remarkable classification accuracy, short event recognition time, and negligible FPR/h are the main advantages of the proposed OVMD-RDCNN-MKRVFLN method over RDCNN, OVMD-RDCNN, and OVMD-RDCNN-KRVFLN methods. The novel RDCNN-MKRVFLN digital architecture is designed and implemented on a high-speed field-programmable gate array (FPGA) hardware environment to design a computer-aided-diagnosis (CAD) system for online epileptic seizure diagnosis. The simplicity, feasibility, and practicability of the proposed method validate the effectiveness of automatic seizure recognition.

Design of a Multichannel Pulser/Receiver and Optimized Damping Resistor for High-Frequency Transducer Applied to SAM System

Scanning acoustic microcopy (SAM) is widely used in biomedical and industrial applications in dermatology, ophthalmology, intravascular imaging, and small animal images, owing to SAM’s ability to photograph small structures with a good spatial resolution. One of the most important devices of this system is the pulser/receiver (P/R) (PRN-300, Ohlabs Corporation, Nam-gu Busan, Republic of Korea), which generates pulses to trigger a high-frequency transducer. This article presents the design of a pulse generator to excite high-frequency transducers with four channels. The characteristics of the pulses, such as time and frequency, can be reconfigured by using a high-speed field programmable gate array (FPGA). The configuration software was developed for communicating with the P/R device via a USB connector for easy, feasible pulse selection and real-time pulse management. Besides that, during the design and implementation of the hardware, we optimized the damping resistor value to reduce the overshoot and undershoot part of the signal, ensuring the best effect on the transducer signal. The test results show that unipolar pulses worked with transducers with frequencies over 100 MHz. The SAM systems can work simultaneously with multiple transducers, and the resulting images have different resolutions of regions.

Optimal Current Allocation Rendering 3-D Magnetic Force Production in Hexapole Electromagnetic Actuation

This article presents the optimal current allocation and the magnetic force production associated with the hexapole electromagnetic actuation, wherein six electromagnets are used to control the magnetic field and exert the 3-D magnetic force on a specified microscopic magnetic particle in the 3-D workspace of the actuating system. It addresses four major issues in the inverse modeling of the multipole electromagnetic actuation, i.e., 1) redundancy; 2) coupling; 3) nonlinearity; and 4) position-dependency, and leads to the accurate and effective 3-D magnetic force production within the specified workspace. Specifically, the optimal inverse modeling of the hexapole electromagnetic actuation is derived to minimize the 2-norm of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$6 \times 1$</tex-math></inline-formula> input current vector when applied to produce the desired 3-D magnetic force to propel the magnetic particle in aqueous solutions. The inverse model is implemented in a high-speed field programmable gate array system to realize the real-time current allocation, which is used to render the feedback stabilization of the magnetic trap. The accurate and effective 3-D force production through the optimal current allocation is experimentally validated.

Design of a FPGA-based controller for power and period measurement in the start range of Dalat Nuclear Research Reactor

This paper introduces a new controller module based on a high-speed field-programmable gate array (FPGA) and digital signal processing (DSP) using moving average (MA) filters for calculation of the reactor power and period at the start range of the Dalat nuclear research reactor (DNRR). The reactor power is proportional to the neutron flux in the reactor core, and the reactor period is the time that the reactor power changes by a factor of 2.718. In the control and protection system (CPS) of the DNRR, the reactor power and period have been monitored by the 8-bit microprocessor controller named BPM-107R. There are two main functions of the BPM-107R controller including 1) measurement and determination of reactor power and period and 2) generation of warning and emergency protection signals by reactor power or/and by reactor period. Those discrete signals will access to the logical processing unit of the CPS to prohibit the upward movement of control rods or to shut down the reactor. The CPS has three BPM-107R controllers corresponding to three independent neutron flux measurement equipment (NFME) channels working by logic voting “2 out-of 3”. Each NFME channel was designed for detection of neutron flux density in the full range from 1×100 to 1.2×1010 n/cm2 ×s, which is divided into two sub-ranges named start range (SR) and working range (WR). The designed FPGA-based controller module was tested using simulated signals as well as signals from the CPS in comparison with the original controller BPM-107R. The experimental results show that the characteristics and functions of the two controllers are equivalent.

Automatic Power Quality Events Recognition Using Modes Decomposition Based Online P-Norm Adaptive Extreme Learning Machine

This article presents an automatic recognition of power quality events (PQEs) by integrating variational mode decomposition (VMD) with Hilbert transform (HT) and the proposed online P-norm adaptive extreme learning machine (OPAELM). The robust parameters estimation capability from the highly nonstationary PQE patterns is presented using VMDHT method and a novel mode selection scheme is introduced based on the correlation coefficient. Three most efficient power quality indices are extracted and fed as an input to train and test the OPAELM classifier with a few existing advanced classifiers. The distinctive modes extraction, low computational burden, robust antinoise performance, short event recognition time, and outstanding recognition capability are the prime superiority expediencies of the VMDHT-OPAELM method. Finally, the proposed method is developed in Xilinx integrated synthesis environment (ISE) Design Suite 14.5 configured with MATLAB/Simulink software environment and implemented in a high-speed field-programmable gate array digital circuitry hardware platform to validate the cogency in real time.

Cavity Simulator for European Spallation Source

European Spallation Source (ESS) will be the brightest neutron source in the world. It is being built in Lund, Sweden. Over 120 superconducting cavities will be installed in the facility, each regulated by an individual low-level radio frequency (LLRF) control system. To reduce the risk of testing the systems on real cavities, a cavity simulator was designed. It reproduces the behavior of superconducting cavities used in the medium and high beta sections of ESS's Linac. The high power RF amplifier and piezo actuators parameters are also simulated. Based on the RF drive and piezo control signals, the cavity simulator generates the RF signals acquired by the inputs of the LLRF control system. This is used to close the LLRF feedback loop in real time. The RF front end of the cavity simulator consists of vector modulators, down-converting circuits, and a set of fast data converters. The cavity response simulation is performed in a high-speed field programmable gate array logic by a dedicated firmware that was optimized to minimize the processing time. The device also generates clock, local oscillator, and the 704.42-MHz reference signals to allow for system tests outside of the accelerator environment. In this paper, the design of the cavity simulator, description of the algorithms used in the firmware, and measurement results of the device are presented.

Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography

Exploiting modification direction (EMD)-based image steganography algorithm has higher embedding efficiency, low distortion, and best security that finds application in secure communication, data protection, access control in digital content distribution, etc., EMD steganography encapsulates secret digit represented in (2n + 1)-ary notational system by increasing or decreasing one of the n cover pixels by one. New high-speed reconfigurable architectures and field programmable gate array (FPGA) implementation of EMD based image steganography algorithms have been proposed. Although, earlier work on FPGA implementation of steganography algorithms offer higher speed, low chip area, and better throughput it usually operates on a fixed number of pixels. The proposed system works well for both arbitrary numbers of pixel groups and variable image resolution. The developed system is capable of embedding a secret message from two to eight-pixel groups with an image resolution of 512 × 512 pixels at a real-time video rate of 549 frames/s.. The complete design is implemented using RTL compliant Verilog code which fits into a single FPGA/ASIC chip with a gate density of two million gates.

Low-Power and High-Speed Deep FPGA Inference Engines for Weed Classification at the Edge

Deep neural networks (DNNs) have recently achieved remarkable performance in a myriad of applications, ranging from image recognition to language processing. Training such networks on graphics processing units (GPUs) currently offers unmatched levels of performance; however, GPUs are subject to large-power requirements. With recent advancements in high-level synthesis (HLS) techniques, new methods for accelerating deep networks using field programmable gate arrays (FPGAs) are emerging. FPGA-based DNNs present substantial advantages in energy efficiency over conventional CPU- and GPU-accelerated networks. Using the Intel FPGA software development kit (SDK) for OpenCL development environment, networks described using the high-level OpenCL framework can be accelerated targeting heterogeneous platforms including CPUs, GPUs, and FPGAs. These networks, if properly customized on GPUs and FPGAs, can be ideal candidates for learning and inference in resource-constrained portable devices such as robots and the Internet of Things (IoT) edge devices, where power is limited and performance is critical. Here, we introduce GPU- and FPGA-accelerated deterministically binarized DNNs, tailored toward weed species classification for robotic weed control. Our developed networks are trained and benchmarked using a publicly available weed species dataset, named DeepWeeds, which include close to 18 000 weed images. We demonstrate that our FPGA-accelerated binarized networks significantly outperform their GPU-accelerated counterparts, achieving a>7-fold decrease in power consumption, while performing inference on weed images 2.86 times faster compared to our best performing baseline full-precision GPU implementation. These significant benefits are gained whilst losing only 1.17% of validation accuracy. In this paper, this is a significant step toward enabling deep inference and learning on IoT edge devices, and smart portable machines such as agricultural robots, which is the target application.

High-precision and fast-response laser power stabilization system for cold atom experiments

An innovative and practical scheme of building laser power stabilization system is proposed by using external-control method. A high-speed Field Programmable Gate Array (FPGA) is used as real-time controller, which makes the closed-loop control period of only 4.175μs and response time for stabilizing process less than 90μs. The typical noises affecting the laser power is analyzed. Experimental results show that the system has a high stability improvement with stability of output laser keeps around 2‰ whether the input laser is free running or frequency scanning, which proves the competent performance to satisfy high request of laser power stability in cold atom experiments. What’s more, the laser power stabilization system can be embedded as a functional module into the FPGA based timing sequence system in cold atom interferometry, which makes the laser power be controllable accurately by the way of time sequence.

High-speed FPGA implementation of orthogonal matching pursuit for compressive sensing signal reconstruction

In this paper, a reconfigurable, high-speed, low-power, and vendor-independent field-programmable gate array (FPGA) implementation of the orthogonal matching pursuit (OMP) algorithm is presented. Unlike existing previous work, the proposed architecture is reconfigurable, that is, the architecture can accept different signal sizes, different sparsity levels, and sampling matrix sizes. Furthermore, the Goldschmidt algorithm is used to implement the fixed point division unit that achieves state-of-the-art performance. To the best of our knowledge, the presented architecture demonstrates the fastest reconstruction times for the standard OMP algorithm on FPGA for high sparsity levels. The proposed design is able to recover a 128-length signal with K = 5 in 7.75 μs and 256-length signals with K = 8 and K = 12 in 23.27 μs and 39.56 μs respectively. The results also show that our design outperforms many other existing FPGA implementations in terms of power consumption.

Optimized Design of Space Solar Array Simulator With Novel Three-Port Linear Power Composite Transistor Based on Multiple Cascaded SiC-JFETs

Space solar array simulators (SSASs), which are used for testing space power systems, generally utilize linear power topologies owing to their fast dynamic performance and satisfactory simulation accuracy. However, to output a medium power level from a linear-power-topology SSAS, multiple parallel linear voltage-controlled current sources are required for addressing the redundant power dissipation, thereby limiting the overall mechanical structure and volume optimization; in addition, the presence of multiple parallel sources results in a complex circuit structure with poor reliability. In this context, in this study, we propose a novel three-port linear power composite transistor as a linear power dissipation device, which is composed of multiple cascaded SiC-JFETs to improve on the above-mentioned shortcomings. The proposed 510-W optimized SSAS requires only eight parallel linear current-source paths to form a linear power stage and uses a high-speed field-programmable gate array (FPGA) digital controller to quickly react to a load step between short circuit and open circuit (the harshest working condition for a solar array simulator) at a 1-kHz stepping frequency. Further, the device can react to a load step between short circuit and the nominal working point at 10-kHz stepping frequency, thus, offering a better dynamic performance over other similar devices.