Optimized Design of Space Solar Array Simulator With Novel Three-Port Linear Power Composite Transistor Based on Multiple Cascaded SiC-JFETs

Abstract

Space solar array simulators (SSASs), which are used for testing space power systems, generally utilize linear power topologies owing to their fast dynamic performance and satisfactory simulation accuracy. However, to output a medium power level from a linear-power-topology SSAS, multiple parallel linear voltage-controlled current sources are required for addressing the redundant power dissipation, thereby limiting the overall mechanical structure and volume optimization; in addition, the presence of multiple parallel sources results in a complex circuit structure with poor reliability. In this context, in this study, we propose a novel three-port linear power composite transistor as a linear power dissipation device, which is composed of multiple cascaded SiC-JFETs to improve on the above-mentioned shortcomings. The proposed 510-W optimized SSAS requires only eight parallel linear current-source paths to form a linear power stage and uses a high-speed field-programmable gate array (FPGA) digital controller to quickly react to a load step between short circuit and open circuit (the harshest working condition for a solar array simulator) at a 1-kHz stepping frequency. Further, the device can react to a load step between short circuit and the nominal working point at 10-kHz stepping frequency, thus, offering a better dynamic performance over other similar devices.