High-speed Digital Design Research Articles

Performance investigation of Ge DLTFET based digital integrated circuit

ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.

Time jitter generation and injection algorithms for high-speed applications.

Time jitter is an important means for evaluating the performance of high-speed communication systems. Current high-speed digital designs require faster edge speeds and smaller effective data windows. Therefore, analysis of the root cause of jitter has become the key factor in determining the success or failure of a design. To analyze the jitter source of the whole link, the jitter is usually extracted and analyzed by software or hardware at the receivers. To verify the accuracy of jitter extraction at the receivers, many instrument manufacturing companies have developed oscilloscope software to inject jitter at the transmitters, but the core algorithms for jitter generation are commercially sensitive and the software cannot inject all types of jitter, particularly bounded uncorrelated jitter, into the pure signals. This paper proposes a software jitter modeling and injection algorithm that can be implemented in MATLAB and includes transmitter test signal modeling, jitter generation, and the injection of various types of jitter. Unlike other research and commercial software, the proposed algorithm enables the injection of various types of jitter, notably bounded uncorrelated jitter, into test signals. This algorithm is suitable for integration into real-time oscilloscopes for jitter generation and injection.

Method for Optimizing Equalization in Nonlinear Signaling Analysis

Nonlinear signaling analysis in nature is a high-dimensional optimization problem, the dimension of which can exceed 100 in today's high-speed digital and mixed-signal design. Optimizing the equalization (EQ) in such a high dimension is even more challenging. In this work, We present a fast method to optimize the equalization in nonlinear high-speed signaling. In this method, the nonlinear responses in the high-dimensional space due to all EQ settings are represented by a rank- $k$ model, where $k$ is in hundreds, which is many orders of magnitude smaller than the original problem dimension. From the rank- $k$ model, we recover the signature responses of each EQ, from which the best EQ setting is determined. Numerical simulations of large-scale real-world nonlinear channels for high-speed signaling have demonstrated the performance of the proposed method.

Suppression of Couplings in High-Speed Interconnects Using Absorbing Materials

In this paper, we propose and investigate two novel applications of absorbing materials to suppress high-frequency couplings in high-speed interconnects. In the first application, absorbing materials are added to connector housing to reduce the noises caused by crosstalk and resonances. In the second application, a low-emission inductor is proposed by applying absorbing materials surrounding the body of an inductor. Full-wave simulations and measurements are performed to verify the proposed techniques. Results show absorbing materials significantly improve the performance of signal/power integrity and greatly reduce electromagnetic interference for high-speed digital system designs.

Advanced Signal Integrity for High-Speed Digital Designs (Hall, S.H. and Heck, H.L.) [Book review

This book can be considered an advanced study in signal integrity. Although some basic material is covered, it is assumed that the reader is well acquainted with basic electromagnetic theory, vector calculus, differential equations, statistics, and transmission-line analysis. The book builds on the traditional knowledge base and covers topics required to design present and future digital systems. The book is divided into 14 chapters and six appendices. The main features of this book can be summarized as follows: visual description of theoretical concepts wherever possible so each chapter includes numerous figures to help reinforce the concepts discussed and rigorous coverage of theory and use of practical examples to demonstrate how to use the theory in practical, real-world applications. There is a high degree of quality with the book's graphs and figures. Six appendices enrich the book with useful equations, identities and conversion formulas. Contemporary signaling systems continue to offer new problems to solve. Engineers who can solve these problems will define the future. This book will equip readers with the necessary practical understanding to contend with contemporary problems in highspeed digital design and provide enough theory to see beyond the book to solve problems that have not yet been encountered.

Stub Effect Mitigations Using Absorbing Materials

A new technology is developed for the mitigation of stub effects in high-speed interconnects. This technology substantially reduces the stub effects for high-speed signaling. It dampens reflected signals on stubs, thus reducing intersymbol interference and harmful coupling, and correcting timing jitter, all typically induced by the stub’s reflected signals. This paper shows two applications for high-speed digital system designs, the mitigation of via stub effects and that of empty connector effects, respectively. However, it is notable that the present method is suitable for reflection suppression for arbitrary types of stubs to improve the signal integrity.

Signal integrity

Welcome to the Signal Integrity Column! In this issue, you will find a very interesting paper on power integrity. In modern high-speed digital designs, power distribution networks (PDNs) using power and ground planes are commonly used where decoupling capacitors are necessary to provide charge for logic transitions and, at the same time, to mitigate the noise generated during device switching. With the continuous increase of data rates and current consumption, as well as the decrease of logic levels, PDN design becomes increasingly challenging. More and more decoupling capacitors would be needed, which presents a seemingly unresolvable conflict with the industry trends for lower cost and more compact design. Prof. Madhavan Swaminathan, a well-known pioneer and expert on power integrity, presents his latest research effort in this paper to address this challenge. I hope his innovative idea can inspire the readers of the EMC Magazine to come up with more ideas to address this fundamental power integrity issue necessary for next generations of high-speed digital designs.

High-frequency and switching performance investigations of novel lightly doped drain and source hetero-material-gate CNTFET

The effects of lightly doped drain and source (LDDS) and hetero-material-gate (HMG) structure on the static characteristics and switching speed performance for a carbon nanotube field effect transistor (CNTFET) have been theoretically investigated by a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green׳s functions (NEGF) solved self-consistently with Poisson׳s equation. A comparison study of electrical characteristics in conventional single-material-gate CNTFET (C-CNTFET), LDDS-CNTFET, HMG-CNTFET and LDDS-HMG-CNTFET structures has been performed. Simulations show that, compared with the other structures, LDDS-HMG-CNTFET significantly decreases leakage current, subthreshold swing, and increases on/off current ratio. In addition, effects of the gate electrode work function of the LDDS-HMG-CNTFET have been studied theoretically. The results indicate that the electron transport efficiency, and the cutoff frequency of the device, can be optimized by reasonably selecting the gate electrode work function. This work illustrates that the proposed LDDS-HMG-CNTFET might be useful for low-power high-speed CNTFET digital design.

New Power Distribution Network Design Method for Digital Systems Using Time-Domain Transient Impedance

In this paper, a power delivery network (PDN) design method using new time-domain transient impedance is proposed for high-speed digital systems designs, with verification by examples and simulations. This method is based on a new triangular pulse representation of a step transient current demand. Compared with the frequency-domain target impedance method, the proposed method results in a much smaller decoupling network, as it only consider the basic power delivery function of the PDN and the time-domain transient impedance has flat impedance response. The proposed time-domain method provides a good preliminary design for large complicated PDN using lumped model analysis.

Signal integrity

Welcome to the Signal Integrity Column! In this issue, you will find a very interesting paper on power integrity. In modern high-speed digital designs, power distribution networks (PDNs) using power and ground planes are commonly used where decoupling capacitors are necessary to provide charge for logic transitions and, at the same time, to mitigate the noise generated during device switching. With the continuous increase of data rates and current consumption, as well as the decrease of logic levels, PDN design becomes increasingly challenging. More and more decoupling capacitors would be needed, which presents a seemingly unresolvable conflict with the industry trends for lower cost and more compact design. Prof. Madhavan Swaminathan, a well-known pioneer and expert on power integrity, presents his latest research effort in this paper to address this challenge. I hope his innovative idea can inspire the readers of the EMC Magazine to come up with more ideas to address this fundamental power integrity issue necessary for next generations of high-speed digital designs.

Differential Extrapolation Method for Separating Dielectric and Rough Conductor Losses in Printed Circuit Boards

Copper foil in printed circuit board (PCB) transmission lines/interconnects is roughened to promote adhesion to dielectric substrates. It is important to characterize PCB substrate dielectrics and correctly separate dielectric and conductor losses, especially as data rates in high-speed digital designs increase. Herein, a differential method is proposed for separating conductor and dielectric losses in PCBs with rough conductors. This approach requires at least three transmission lines with identical, or at least as close as technologically possible, basic geometry parameters of signal trace, distance-to-ground planes, and dielectric properties, while the average peak-to-valley amplitude of surface roughness of the conductor would be different. The peak-to-valley amplitude of conductor roughness is determined from scanning electron microscopy images.

Transmission Lines in Digital Systems for EMC Practioners (Paul, C.R.; 2012) [Book review

This brief and comprehensive book covers the set of transmission line skills required by high speed digital designers. It is very down to earth and practical, containing much useful information for the engineer/designer. Although there are many books on transmission lines, this book emphasizes digital transmission lines, a subject where there is currently limited information available. Three things make this book unique: It covers digital transmission sysetms, it emphasizes transmission lines with rectangular cross-sections, and it has an extensive discussion of crosstalk between transmission lines.

Extraction of Clock Driver Output Impedance for Signal Integrity Design

With increasing clock speed in high-speed digital design, proper impedance matching between the printed circuit board trace and the clock driver output is crucial for signal integrity design. Adding a series output resistor is a common technique to match a clock driver output to a high-speed signal trace for its simplicity and ease of implementation. The selection of the value of the series output resistor requires known output impedance of the clock driver, which is not always readily available. Based on an in-circuit measurement approach, a method to extract the output impedance of any clock driver under its actual operating condition has been developed. With the known output impedance of the clock driver, precise selection of the series resistor value for impedance matching purpose has become a relatively simple task without the usual trial-and-error process.

Essential Principles of Signal Integrity

High-speed digital design is driven by the analog effects of interconnects. These are fundamentally driven by the overlap of Maxwell's equations and board design. While simulations can help optimize a design, it is still fundamentally an engineer's design intuition that establishes the starting place. The earlier in the design process problems can be identified and designed out, the shorter the devel opment time, the lower the development cost, and the greater the chance of an acceptable design on the first pass. The stronger your signal integrity design intuition, the more effective you will be in this era of high-speed products.

High-Speed Digital Design

High-speed digital design and microwave design share a rich heritage of electrical engineering theory, yet, key differences separate these two fields and the people that work in them.

Differential Via Modeling Methodology

This paper describes a novel method of modeling the differential via on multilayered printed circuit boards (PCBs) used in high-speed digital designs based on the analytical equations for characteristic impedance and effective dielectric constant. In the absence of measured or electromagnetic simulated data traditionally needed to extract these parameters, this method can quickly and efficiently predict the behavior of the differential via holes on PCBs using a circuit simulator.

Experimental results for low-jitter wide-band dual cascaded phase locked loop system

Jitter is a matter of great concern for high-speed digital designers because of its ability to degrade the overall; system performance. Designing a low-jitter and wide-band phase locked loop (PLL) system is of practical importance because of its application in high speed digital systems. This paper presents experimental results of a low-jitter wideband dual cascaded PLL system using a single crystal oscillator. The first PLL employs a voltage controlled crystal oscillator (VCXO) to eliminate the input jitter whereas the second PLL provides wide bandwidth. Field Programmable Gate Array (FPGA) is used to generate a jittered clock source which is then passed through the proposed system to achieve wideband and low-jitter signal. Experimental results are presented to validate the proposed technique for different carrier frequencies.

PLANAR TRANSMISSION LINE METHOD FOR CHARACTERIZATION OF PRINTED CIRCUIT BOARD DIELECTRICS

Abstract|An efiective approach to characterize frequency-dispersivesheet materials over a wide RF and microwave frequency range basedon planar transmission line geometries and a genetic algorithm isproposed. S -parameters of a planar transmission line structure witha sheet material under test as a substrate of this line are measuredusing a vector network analyzer (VNA). The measured S -parametersare then converted to ABCD matrix parameters. With the assumptionof TEM/quasi-TEM wave propagation on the measured line, as wellas reciprocity and symmetry of the network, the complex propagationconstant can be found, and the corresponding phase constant andattenuation constant can be retrieved. Attenuation constant includesboth dielectric loss and conductor loss terms. At the same time,phase term, dielectric loss and conductor loss can be calculatedfor a known transmission line geometry using corresponding closed-form analytical or empirical formulas. These formulas are used toconstruct the objective functions for approximating phase constants,conductor loss and dielectric loss in an optimization procedure basedon a genetic algorithm (GA). The frequency-dependent dielectricproperties of the substrate material under test are represented asone or a few terms following the Debye dispersion law. Theparameters of the Debye dispersion law are extracted using theGA by minimizing the discrepancies between the measured and thecorresponding approximated loss and phase terms. The extracted datais verifled by substituting these data in full-wave numerical modelingof structures containing these materials and comparing the simulatedresults with experimental.1. INTRODUCTIONDevelopment of simple and robust methods for wideband extractionof frequency characteristics of planar sheet materials for variouselectromagnetic applications is an important present-day problem. Inparticular, characterization of dielectric substrates for printed circuitboards (PCBs) is vital to achieve the flrst-pass success in modern high-speed digital system designs. When the on-board data rate is in theGbps (gigabits per second) range or higher, traces and discontinuitiesincluding vias, AC coupling pads, and trace bends on a signal path haveto be modeled to catch the channel response accurately [1{3]. A staticfleld solver is not su–cient to model these discontinuities and traces,and full-wave modeling tools have to be used. To build the full-wavemodel for a given signal path, the detailed structures are known, butthe well-represented dielectric material properties of the correspondingsubstrates are unknown. In general, the dielectric properties (relative

Delaunay–Voronoi Modeling of Power-Ground Planes With Source Port Correction

An efficient Delaunay-Voronoi modeling of the power-ground planes suitable directly for SPICE compatibity is proposed to deal with the ground bounce noise and decoupling capacitors placement problems for the high-speed digital system designs. The model consists of virtual ports and triangular meshes with the lumped circuit elements, in which all the element values can be related to the mesh geometry shape by the analogy between the circuit equations and Maxwell's equations. Since the analogy fails to apply due to the singular fields near the input/output pins, the via effect of driving and sensing ports is not negligible and an analytical expression from the Hankel function is thus presented for the correction term. A simple rule has been investigated for the model with minimum lumped circuit elements to accurately represent the power-ground planes over the frequency range of interests. The full-wave simulation and measurement results verify the good correlations with the proposed models for the impedance responses of regular and defective plane shapes.

Transient Signals on Transmission Lines: An Introduction to Non-Ideal Effects and Signal Integrity Issues in Electrical Systems

This lecture provides an introduction to transmission line effects in the time domain. Fundamentals including time of flight, impedance discontinuities, proper termination schemes, nonlinear and reactive loads, and crosstalk are considered. Required prerequisite knowledge is limited to conventional circuit theory. The material is intended to supplement standard textbooks for use with undergraduate students in electrical engineering or computer engineering. The contents should also be of value to practicing engineers with interests in signal integrity and high-speed digital design.