High-speed Digital Design Research Articles

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS

This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-VT MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

This paper provides evidence that, as a result of constant-field scaling, the peak fT (approx. 0.3 mA/mum), peak fMAX (approx. 0.2 mA/mum), and optimum noise figure NFMIN (approx. 0.15 mA/mum) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers

High-Speed Digital System Design

High-Speed Digital System Design bridges the gap from theory to implementation in the real world. Systems with clock speeds in low megahertz range qualify for high-speed. Proper design results in quality digital transmissions and lowers the chance for errors. This book is for computer and electrical engineers who may or may not have learned electromagnetic theory. The presentation style allows readers to quickly begin designing their own high-speed systems and diagnosing existing designs for errors. After studying this book, readers will be able to: Design the power distribution system for a printed circuit board to minimize noise Plan the layers of a PCB for signals, power, and ground to maximize signal quality and minimize noise Include test structures in the printed circuit board to easily diagnose manufacturing mistakes Choose the best PCB design parameters such a trace width, height,and routed path to ensure the most stable characteristic impedance Determine the correct terminati n to minimize reflections Predict the delay caused by a given PCB trace Minimize driver power consumption using AC terminations Compensate for discontinuities along a PCB trace Use pre-emphasis and equalization techniques to counteract lossy transmission lines Determine the amount of crosstalk between two traces Diagnose existing PCBs to determine the sources of errors

High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition

Asymmetric slope differential CMOS (ASD-CMOS) and asymmetric slope differential dynamic logic (ASDDL) surpass the highest speed that conventional CMOS logic circuits can achieve, resulting from deeply shortened rise time along with relatively prolonged fall time. ASD-CMOS is a static logic and ASDDL is a dynamic logic without per-gate synchronous clock signal, each of which needs two-phase operation as well as differential signaling, however, interleaved precharging hides the prolonged fall time and BDD-based compound logic design mitigates area increase. ASD-CMOS 16-bit multiplier in a 0.18-μm CMOS technology demonstrates 1.78 nsec per an operation, which reaches 34% reduction of the best delay time achieved by a multiplier using a CMOS standard cell library that is conventional yet tuned to the optimum in energy-delay products. ASDDL can be superior to DCVS-DOMINO circuits not only in delay time but also in area and even in power. ASDDL 16-bit multiplier achieves delay and power reduction of 4% and 20%, respectively, compared with DCVS-DOMINO realization. A prototype ASD-CMOS 16-bit multiplier with built-in test circuitry fabricated in a 0.13-μm CMOS technology operates with the delay time of 1.57 nsec at 1.2 V.

Efficient Computation of Z-parameter for the Rectangular Planar Circuit Analysis

The conventional eigen-mode expansion method is a commonly used approach to compute Z-parameter of a rectangular planar circuit. However a double infinite series in the method limit its computation efficiency. This paper develops a novel convergence-accelerating algorithm to improve the efficiency, which is based on a trigonometric Fourier series formula and the η-algorithm. The trigonometric Fourier series formula transforms the double infinite series into a single one and the η-algorithm can accelerate the convergence of the single infinite series. The technique has high efficiency and good accuracy, which are testified by a numerical example. I. Introduction With the operating frequencies increasing and working voltage decreasing in high-speed digital systems, the model and design of Power/Ground (P/G) planes are becoming more and more critical. In order to develop a systematic P/G design strategy, the fundamental properties of P/G plane structures need to be explored. The conventional eigen-mode expansion method is a commonly used approach to compute Z-parameter of a rectangular planar circuit. However the formula in the method involves a summation of a double infinite series, which may consume much time and computer storage to obtain sufficiently good accuracy. To improve the computation efficiency, this paper proposes a new convergence-accelerating algorithm, which is based on a trigonometric Fourier series formula [1] and the η-algorithm [2][3]. The formula was first applied to the eigenmode expansion method in paper [4], but it adopted another accelerating technique. The η-algorithm was first used to compute the Z-parameters of planar circuits in paper [5][6], but it was directly applied to the 2-D case, which was difficult to be comprehended, and its computation effi ciency was limited by the two series. In this paper, the double infinite series is first transformed into a single one by the trigonometric Fourier series formula and then the η-algorithm is adopted to accelerate the convergence of the single infinite series. The technique is easy to catch on and has high efficiency and good accuracy, which are testified by a numerical example. The organization of this paper is as follows. The eigen-mode expansion method is introduced in Section II. Section III presents the new convergence-accelerating algorithm in detail. To prove its efficiency and accuracy, in Section IV the new technique is adopted to a example. Section V draws a conclusion.

Electromagnetic compatibility issues in mobile computing

ELECTROMAGNETIC compatibility (EMC) is the engineering of electronic components and systems to ensure the overall functioning in a complex electromagnetic environment. Historically, this has included many aspects of the design, such as compliance with electromagnetic interference (EMI) regulatory standards, and insuring immunity of electronics to the electrical noise, i.e., interference generated by a neighboring system or external source. Electrostatic discharge (ESD) is one aspect of electronic immunity that can lead to failure at the IC, module, or system level that is again becoming a major concern in electronic design. EMC has traditionally also included wave-shaping and ensuring signal fidelity, as well as design of an adequately low-noise power distribution network to minimize EMI, and not compromise signal fidelity. Historically, EMC has been characterized as a “copper-tape-and-ferrites,” trial-and-error discipline that reflects a postdesign approach to EMC. As design cycles have decreased, this approach to EMC has changed dramatically over the course of the past five to seven years. Within the commercial electronics community, the need and demand for EMC computer-aided design tools grew as rapidly as the design cycles decreased, and the complexity and data rates of designs increased. However, suitable tools had not been developed and, inmany cases, the underlying noise coupling and immunity physics were not well understood. In large part, this state of affairs resulted from a lack of funding for more basic research and CAD tool development, and the complexity of the problem. The immediate demand for sophisticated EMC design tools that were undeveloped gave rise to focused research in EMC to understand the coupling physics and develop design methodologies and tools in industry and academia alike. Many individual companies have made significant investments in in-house EMC research, as well as funding of university research. The demand for a basic understanding of interference coupling physics, as well as design approaches and tools led to the development of focused EMC research within the UMR EMCConsortium at the University of Missouri-Rolla, as well as a significant research emphasis in other electronics and packaging centers such as the Packaging Research Center at Georgia Tech and the CALCE Electronic Products and Research Center at the University of Maryland. The field of EMC has grown into a number of specialty areas, in particular, in the past five years, which reflects the present challenges associated with electronic design. This has resulted in part from increasing data rates and clock frequencies, decreasing logic levels resulting from increased power requirements, decreasing design densities, mixedsignal analog/digital designs within the same package, and higher frequency switching power supplies, among a host of other issues. There is still a significant need for a basic understanding of EMC in many aspects of high-speed digital and mixed-signal design including EMI (including radio-frequency interference (RFI)), immunity (including ESD), signal integrity (SI), and power integrity, in particular, at the IC, and IC substrate and packaging level. In addition, the need for modeling approaches and CAD tools in all areas of electromagnetic compatibility is acute. In an engineering design environment, the models and tools must be suitable for rapid computation and be within the expertise of a component or system designer to use. In practice, this reduces to circuit and transmission-line modeling, i.e., the typical SPICE-type environment. The performance of first-pass engineering design validation hardware is often plagued by undesirable parasitics that compromise the signal fidelity and/or level, and dominate the coupling in the case of EMI and immunity. The coupling is through the electric field (capacitive coupling), magnetic field (inductive coupling), or through a common current return path, intended or unintended. In short, EMC is “about the things that are not on the circuit schematic,” i.e., parasitic effects. There is a critical need for design methodologies and CAD tools that are based on well-understood parasitic effects and coupling physics, and can anticipate or extract suitable parasitic lumped circuit element models from a layout geometry. Presently, there are no such mature CAD tools. There are well-developed tools for the numerical solution of Maxwell’s equations, RF circuit design tools, and circuit simulation tools. However, tools for anticipating parasitic effects are predominantly still at a beginning stage of development. To use a literature analogy, the complexity of the problem demands a solution with the sophistication of Tolstoy, but the available tools are at a grade-school primer stage of development. Among the most challenging of electronics designs for EMC are those associated with mobile computing. These designs are typically battery powered with no real-time generation, and are low-power. In addition, the designs IEEE TRANSACTIONS ON MOBILE COMPUTING, VOL. 2, NO. 4, OCTOBER-DECEMBER 2003 273

On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits

High-speed digital design is becoming increasingly analog. In particular, interconnect response at high frequencies can be nonmonotonic with porch steps and ringing. Crosstalk (both capacitive and inductive) can result in glitches on wires that can produce functional failures in receiving circuits. Most of these important effects are not addressed with traditional automatic test pattern generation (ATPG) and built-in self-test (BIST) techniques, which are limited to the binary abstraction. In this work, we explore the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms on selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve 10-ps timing accuracy. High-speed samplers are combined with delay-locked loops (DLLs) and a simple 8-bit analog-to-digital converter (ADC) to convert the waveforms into digital data that can be incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to incorporate these oscilloscopes with a high-frequency interconnect structure in a TSMC 0.25-/spl mu/m process. The layout was extracted using Cadence's Assura RCX-PL extraction engine, enabling a comparison between simulated and measured results.

Minimum buffered routing with bounded capacitive load for slew rate and reliability control

In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise. Bounding load capacitance also improves reliability with respect to hot-carrier oxide breakdown and AC self-heating in interconnects, and guarantees bounded input rise/fall times at buffers and sinks. This paper introduces a new minimum-buffer routing problem (MBRP) formulation which requires that the capacitive load of each buffer, and of the source driver, be upper-bounded by a given constant. Our contributions are as follows: We give linear-time algorithms for optimal buffering of a given routing tree with a single (inverting or noninverting) buffer type. For simultaneous routing and buffering with a single noninverting buffer type, we prove that no algorithm can guarantee a factor smaller than 2 unless P=NP and give an algorithm with approximation factor slightly larger than 2 for typical buffers. For the case of a single inverting buffer type, we give an algorithm with approximation factor slightly larger than 4. We give local-improvement and clustering based MBRP heuristics with improved practical performance, and present a comprehensive experimental study comparing the runtime/quality tradeoffs of the proposed MBRP heuristics on test cases extracted from recent industrial designs.

The InP-HEMT IC Technology for 40-Gbit/s Optical Communications

We present the outline of the InP HEMT IC technology. This technology realizes InP HEMT digital ICs for 40-Gbit/s optical fiber communication systems through the integration of 0.1-μm-gate-length HEMTs, vertical diodes, capacitors, and WSiN resistors with two level interconnections. This paper describes the high-speed digital IC circuit design and fabrication in InP HEMT technology for 40-Gbit/s/channel optical communication systems. Some results on InP HEMTs' reliability are also covered. Basic circuit design techniques utilizing SCFL topology and fundamental circuit elements of the selector and D-type flip-flop are discussed in detail. The basic digital ICs of MUX, D-FF, and DEMUX ICs fabricated with 0.1-μm-gate InP HEMTs successfully operated up to 50 Gbit/s in the packaged modules. These IC modules offer large speed margins for the 43-Gbit/s OTU-3 data rate. In order to develop cost-effective optical transmitters and receivers, we designed a PLL-based CDR with a full-rate architecture. The fully monolithic integrated CDR exhibited error-free operation for 231-1 PRBS data signal at the OTU-3 bit rate of 43.0184 Gbit/s. Four-bit MUX and DEMUX ICs are other key components, and could be implemented by using InP HEMT technology. Additionally, we describe InP-IC fabrication technology with two-level inter-connection. This is already fully matured for 40-Gbit/s SSI fabrication. The uniform FET characteristics and high-yield passive component fabrication technologies support this degree of maturity. InP HEMT lifetime is 107 hours at l00°C. These results prove the InP HEMT IC fabrication technology presented here, to be highly reliable. These investigation show that robust performance and yield when realizing SSI and MSI 40-Gbit/s functions.

Modeling of simultaneous switching noise in high speed systems

Simultaneous switching noise (SSN) has become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex: due to the thousands of interconnects that need to be analyzed. This is because a system level modeling approach is necessary that combines the chip, package and board level interactions. This paper presents an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition theory. This approximation is valid at frequencies where skin effect is dominant. Simulation results are compared with the measurements on a test vehicle, verifying the validity of the method. In addition a system has been simulated to compute SSN, showing the application of this method for complex systems.

Modeling DC power-bus structures with vertical discontinuities using a circuit extraction approach based on a mixed-potential integral equation

The DC power-bus is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation is presented herein to model arbitrary multilayer power-bus structures with vertical discontinuities that include decoupling capacitor interconnects. Green's functions in a stratified medium are used and the problem is formulated using a mixed-potential integral equation approach. The final matrix equation is not solved, rather, an equivalent circuit model is extracted from the first-principles formulation. Agreement between modeling and measurements is good, and the utility of the approach is demonstrated for DC power-bus design.

High-speed digital system design: a handbook of interconnect theory and design practices

From the Publisher: An understanding of high-speed interconnect phenomena is essential for digital designers who must deal with the challenges posed by the ever-increasing operating speeds of today's microprocessors. This book provides a much-needed, practical guide to the state of the art of modern digital system design, combining easily accessible explanations with immensely useful problem-solving strategies. Written by three leading Intel engineers, High-Speed Digital System Design clarifies difficult and often neglected topics involving the effects of high frequencies on digital buses and presents a variety of proven techniques and application examples. Extensive appendices, formulas, modeling techniques as well as hundreds of figures are also provided.

High-speed digital system design, a handbook of interconnect theory and design practices.[Book Review

High-speed digital system design, a handbook of interconnect theory and design practices.[Book Review

DC power-bus modeling and design with a mixed-potential integral-equation formulation and circuit extraction

The application of a circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) for DC power-bus modeling in high-speed digital designs is detailed. Agreement with measurements demonstrates the effectiveness of the approach. Dielectric losses are included into the calculation of the Green's functions, and thus, incorporated into the rigorous first principles formulation. A SPICE model is then extracted from the discretized integral equation. A quasistatic approximation is used for the Green's functions to keep the extracted circuit elements frequency independent. Previous work has established a necessary meshing criterion in order to ensure accuracy for a given substrate thickness and dielectric constant to a desired frequency. Several power-bus design issues, such as surface mount decoupling and power-plane segmentation, were investigated using the modeling approach. The results and discussions illustrate the application of the method to DC power-bus design for printed circuit and multi-chip module substrates.

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

DC power-bus design using FDTD modeling with dispersive media and surface mount technology components

DC power-bus modeling in high-speed digital design using the finite-difference time-domain (FDTD) method is demonstrated herein. The dispersive character of the dielectric layers used in printed circuit board substrates is taken into account in this study. In particular, FR-4 is considered. The complex permittivity of the dielectric is approximated by a Debye model. A wide-band frequency response (100 MHz-5 GHz) is obtained through a single FDTD simulation. Good agreement is achieved between the modeled and measured results for a typical dc power-bus structure with multiple surface mount technology (SMT) decoupling capacitors placed on the printed circuit board (PCB). The FDTD method is then applied to investigate some general approaches of power-bus noise decoupling.

20-40-Gbit/s-CLASS GaAs MESFET DIGITAL ICs FOR FUTURE OPTICAL FIBER COMMUNICATIONS SYSTEMS

This paper describes recent advances in high-speed digital IC design technologies based on GaAs MESFETs for future high-speed optical communications systems. We devised new types of a data selector and flip-flops, which are key elements in performing high-speed digital functions (signal multiplexing, decision, demultiplexing, and frequency conversion) in front-end transmitter/receiver systems. Incorporating these circuit design technologies with state-of-the-art 0.12 μm gate-length GaAs MESFET process, we developed a DC-to-44-Gbit/s 2:1 data multiplexer IC, a DC-to 22-Gbit/s static decision IC, and a 20-to-40-Gbit/s dynamic decision IC. The fabricated ICs demonstrated record speed performances for GaAs MESFETs. Although further operating speed margin is still required, the GaAs MESFET is a potential candidate for 20- to 40-Gbit/s class applications.

Use of modular coding for high-speed digital filter design

Use of modular coding for high-speed digital filter design

Variable supply-voltage scheme for low-power high-speed CMOS digital design

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-/spl mu/m CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

Packaging impact on switching noise in high-speed digital systems

Owing to the ever-increasing clock frequency in digital circuits and systems, simultaneous switching noise (SSN), caused by fast rise/fall pulse edges in combination with parasitic inductance in the power supply distribution network, is becoming a severe problem in many high-speed digital system designs. It is quantitatively shown that the influence of SSN, which is negligible when the rise/fall time is long (> 5 ns), becomes a critical factor, limiting system performance in the sub-nanosecond rise time region. Based on theoretical analyses and computational simulations in respect to various packaging techniques, technical solutions and design guidelines for reducing SSN are summarised.