High-speed Data Bus Research Articles

Interactive Technology between OCS and OMS Based on Artificial Intelligence Technology

In order to realize the interaction between OCS and OMS. The author gives the artificial intelligence technology to analyze the interaction technology between CS and OMS. High-speed data bus and general service bus are deployed in OCS and OMS systems respectively. Through real-time data interaction, service invocation such as static security analysis, sensitivity analysis and the construction of integrated operation and maintenance management subsystem, the cross-region interaction method is validated. The test results show that through the construction of this scheme, it not only meets the secondary security requirements of power, but also improves the real-time and reliability of information exchange between OMS and OMS, and ensures the effective circulation of various dispatching services.

Research on Testing of Optical Fiber Wavelength Division Multiplexing System

In order to meet the requirement of long-distance high-speed data bus for information transmission in vehicles, optical fiber wavelength division multiplexing (FWDM) technology is used to realize the transmission of multiple optical signals by connector. Although wavelength division multiplexing technology has been widely used in the field of communication, the adaptability of the real-time control system needs to be further studied. In this paper, a prototype of the optical fiber wavelength division multiplexing system is tested and the test results are preliminarily studied, which provides a basis for evaluating transmission reliability margin and analyzing system failure.

基于EtherCAT高速数据总线的烟雾报警系统

基于EtherCAT高速数据总线的烟雾报警系统

A Single-Chip 4K 60-fps 4:2:2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K

A professional-image-quality video encoder LSI for broadcasting and content distribution has been developed with single-chip 4K 60-fps 4:2:2 high-efficiency video coding (HEVC) encoding capability and 8K ultrahigh definition television scalability. Edge-based intramode pruning and statistically adaptive multiblock-size motion estimation (ME) efficiently reduce HEVC’s high computational complexity for real-time processing, while a deeply centralized-mode decision framework maintains high compression performance. Internal reference image caches with 797-Gb/s image feed capability support the 768-GOPS ME computation of distributed motion vector search. Interchip pictures and data exchange features with high-speed data buses are also used for multichip 8K encoding configuration. A subjective evaluation showed that the proposed encoder LSI maintained the same visual quality as an encoder LSI complying with the previous standard while reducing bit rate by 40%. The chip was designed and fabricated in a 28-nm CMOS technology and used to build industry-leading 4K and 8K broadcasting systems.

1394b Multi-Subnet Algorithm Based on the Theory of Queues

The high-speed serial data bus, IEEE-1394b, is one of the most popular bus standards in avionics system, but it cannot achieve multiplexing transmission. To solve this problem, a multi-subnet partition algorithm based on the Theory of Queues (TQ) is implemented in this paper. By utilizing matrix to describe the system topology and transmission bandwidth between nodes, the algorithm can efficiently result in the minimum delay system topology. Simulation results show that the algorithm can successfully determine the topologies with minimum delay for different data transmission bandwidth matrix of the multi-network system, which are consistent with the analysis. This verifies the correctness of the algorithm.

Performance evaluation of IEEE 1394b serial bus with Deterministic and Stochastic Petri Nets

IEEE 1394b is a high-speed data bus that is widely used in local area networks and consumer electronics. To best utilize this data bus, we need to fully understand its performance. To evaluate its performance for both isochronous and asynchronous data transfers, we model the IEEE 1394b bus using Deterministic and Stochastic Petri Nets (DSPNs), and conduct simulations using TimeNET 4.0. Using the DSPNs model, we simulate both the average waiting times of isochronous and asynchronous packets. From the simulation results, we determine the factors that influence performance, such as throughput, size of packets, arrival rate of packets, number of isochronous channels, and bus configuration.

Discussion on SFODB Application for Spacecraft Data Management

SFODB(Spaceborne Fiber Optic Data Bus)的提出主要是为解决飞行器内部有效载荷数据率日益提高这一迫切问题,它是一种基于商用异步传输模式(ATM)的高速航天数据总线技术,适合于空间探测器的海量数据包传输.其物理拓扑是由光纤链路连接多个FBIU单元以及单个CFBIU单元组成的环形网络,各节点之间的距离不超过100m,基本数据率可从200Mbit·s^-1变化至1Gbit·s^-1,并具有极高的实时性和可靠性,相比其他总线网络规模小,性能更优.针对SFODB的特性,分析了其发展现状和技术途径,提出了一种在飞行器内部采用SFODB总线作为主干网的数据网络架构,该网络能完成飞行器内部不同数据率载荷的分类分层可靠传输.在此基础上对SFODB的研究与应用提出了建议.

Crosstalk Simulation Based on Full Wave S-Parameter Extraction Method between High-Speed Signals

Crosstalk between high speed parallel bus signals is one of the most important signal integrity(SI) issues. In this article, a crosstalk simulation method based on full-wave scattering parameters extraction for transmission lines is researched. First, the coupling mechanism between transmission lines is analyzed using S-Parameter network theory and a fast frequency-domain method for crosstalk calculation is introduced. Then based on this method, some basic rules of crosstalk are studied in details and the method is validated by simulation results which agree well with those of RLGC model. At the end of this paper, a practical crosstalk simulation example between high speed data bus signals on a 8-layered printed circuit board is demonstrated step by step.

Exploiting Graphic Processing Units Parallelism to Improve Intelligent Data Acquisition System Performance in JET's Correlation Reflectometer

The performance of intelligent data acquisition systems relies heavily on their processing capabilities and local bus bandwidth, especially in applications with high sample rates or high number of channels. This is the case of the self adaptive sampling rate data acquisition system installed as a pilot experiment in KG8 B correlation reflectometer at JET. The system, which is based on the ITMS platform, continuously adapts the sample rate during the acquisition depending on the signal bandwidth. In order to do so it must transfer acquired data to a memory buffer in the host processor and run heavy computational algorithms for each data block. The processing capabilities of the host CPU and the bandwidth of the PXI bus limit the maximum sample rate that can be achieved, therefore limiting the maximum bandwidth of the phenomena that can be studied. Graphic processing units (GPU) are becoming an alternative for speeding up compute intensive kernels of scientific, imaging and simulation applications. However, integrating this technology into data acquisition systems is not a straight forward step, not to mention exploiting their parallelism efficiently. This paper discusses the use of GPUs with new high speed data bus interfaces to improve the performance of the self adaptive sampling rate data acquisition system installed on JET. Integration is sues are discussed and performance evaluations are presented.

The Driver Design for SpaceWire Communication Device Based on Embedded Linux

SpaceWire is becoming a popular solution for satellite high-speed data buses, because it is a simple standard that provides great flexibility for a wide range of system requirements. This article introduces the driver design for the SpaceWire communication device based on embedded Linux, including the analysis of the driver structure, the design of the interfaces between the upper and lower layers and the responding strategy for interrupts. In the realization link, we choose a mainstream developing platform and realize a camera capturing system for testing, and analyse the test result.

Using Evolutionary Algorithms for Signal Integrity Assessment of High-Speed Data Buses

Today's high performance computer systems must have fast, reliable access to memory and I/O devices. Unfortunately, inter-symbol interference, transmission line effects and other noise sources can distort data transfers. Engineers must therefore determine if bus designs have signal integrity--i.e., can transfer data with minimal amplitude or timing distortion. One method of determining signal integrity on buses is to conduct a set of data transfers and measure various signal parameters at the receiver end. But the tests must be conducted with stressful test patterns that maximize noise to help identify any potential problems. In this paper we describe how an evolutionary algorithm was used to evolve test patterns for use in intrinsic testing.

Design and VHDL simulation of a special high speed spaceborne bus controller

The application of high speed data bus on the satellites having several remote sensors could not only satisfy the demand of high speed data transfer, but also could reuse the equipment at both the component and subsystem levels for other space missions, thus reducing the costs of on-board processing system integration. In this article, a special high speed data bus with simple interfaces is chosen for transferring the data produced by remote sensors and other instrumentations. First, the function and the structure of the data bus are discussed carefully. And then, the bus controller, which is a key module of the data bus, is designed. At last, the function and performance of the bus controller are verified by VHDL simulation.

Fuzzy Control of Coding Schemes for Reducing Energy Dissipation in Off-Chip Buses

In this paper, we proposed an high-speed and low-power off-chip data bus interface based on the best coding schemes in this hard operative condition. We analyzed the clustered bus invert method and the bus switch coding, a newly proposed approach based on bus lines logically re-ordered. We proposed an high speed and low-power bus interface based on the combined employment of these two approaches controlled by a 9-rules Takagi-Sugeno analog fuzzy controller. The controller analyzes the binary traffic statistical property changing on the fly the used coding scheme. The fuzzy controller has been designed taking care of total energy dissipation such to do not compromise the benefit of coding approaches. The controller is able also to re-configure the bus switch sub-section in an operative condition where original approach introduces strong power losses. We demonstrated the effectiveness of the approach designing at transistor level the analog fuzzy controller and the digital part of the bus interface. Simulation conducted with H-SPICE and NANOSIM confirmed the bus interface is the optimal trade-off for reducing dynamic energy in off-chip buses.

110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock

Simultaneous bi-directional transceiver logic (SBTL) doubles data bandwidth because data are transmitted simultaneously in each direction over one wire. The technique has enhanced the cost performance of a commercial high-end UNIX server because the number of LSI signal pins, board signal nets, and connectors have decreased by half. And the SBTL speed can improve to more than 1 Gb/s per pin by using advanced process and circuit technology. The previous high frequency interface uses source-synchronous transmission. But a transmission that is not synchronized with a system clock requires long latency time of several cycles for clock synchronization and data recognition at the receiver LSI. A large interface circuit for the clock synchronization is a disadvantage. Therefore, the SBTL technique synchronized with a system clock has been developed in this work to minimize the latency time even at a high frequency of 1.1 Gb/s per pin. Also, a high-speed signal pin count per LSI is important. Low-noise technique of an output buffer circuit and a package has been developed to get a 100 B high-speed data bus per LSI. The maximum data bandwidth is 110 GB/s per LSI.

Proving properties of a new high speed data bus with predicate/transition nets

Frame Synchronized Ring (FSR-bus) is a new high speed interconnection network, developed for a wide range of real time applications. The medium access control (MAC) algorithm of the FSR has been analyzed with analytical models and simulations. However, these methods have not been powerful enough for proving some interesting properties of the algorithm. In this paper we explain, how predicate/transition (Pr/T) nets can be used in the modeling of the FSR-bus. In addition, we prove the deadlock freeness and the fairness of the MAC by analyzing the Pr/T-net model of the FSR.

Dual token passing network configuration for hard real time control applications

A novel technique is described for improving the response time of a token passing network without resorting to high transmission rates. A token passing network, known as the HRT-Net (hard real time network) operating at 1 Mbit/s, is proposed and evaluated. It is shown that the HRT-Net provides superior response time characteristics when compared with industrial standard networks such as the mini-MAP and the SAE high speed data bus.

The fiber-optic high-speed data bus for a new generation of military aircraft

The avionic suite for the next generation of military aircraft is being designed with component and module commonality in mind in order to control recurring costs and capitalize on economy of scale. The backbone of the suite fashioned out of these modular building blocks is the fiber-optic bit-serial time-division multiplexed high-speed data bus (HSDB), operating at 50 Mb/s, which provides command and control communications among most of the aircraft subsystems and can be used to provide communications for a fly-by-light flight-control system or for the block transfer of data between mass memories and data processors. The fiber-optic HSDB is examined from the top down, beginning with an overview of the evolution of avionic architectures. A review is given of the standardization activity associated with development of the network, the protocols chosen to implement the desired communication functions, configuration options, and the fiber-optic components used in the bus interfaces or other active nodes of the network. It is believed that the utility of the bus extends beyond aircraft to spacecraft, ships, and land vehicles. >

Intraplane guided wave massive fanout optical interconnections

One-to-30 guided wave optical interconnections are demonstrated at 632.8 nm using a highly multiplexed waveguide volume hologram. This technology is capable of providing intrachip and intrawafer optical interconnections. The theoretical limit of the fanout number is addressed and experimentally confirmed. The measured data show that the diffracted beams have an average diffraction efficiency of 2.3% with ±0.2% variation. The demonstrated results can save surface space of electronic chips and also provide a large fanout capability due to the high index modulation of the volume hologram. Further applications based on this technology are very promising. Head-up display, high-speed optical data bus, surface enhanced Raman spectrometer, and optical sensors are some of the attractive ones.

Data system with distributed processing for a next generation satellite

This paper describes a data system with distributed processing for a next generation satellite system that is at a conceptual design stage. It is a constellation of identical observation satellites with payloads that produce a high amount of sensor data, as well as housekeeping data. The early design had two data buses driven by two different types of data—command, control, and telemetry (C T) data, and burst-type sensor data. The CT messages led to a low-speed IMbps CT bus; the sensor data characterized by long-length messages led to an asynchronous 50 Mbps high-speed data bus. The architecture of the buses and the computer simulation of the traffic flow on these buses is described. To support real-time operations of the spacecraft, the data system is required to support the peak load of message flows. The key factors are message frequencies, priorities, lengths, and data latency. To verify the performance, computer simulations were performed, based on the expected traffic and the selected bus protocols for the buses. The results show that the design provides an ample margin in bus bandwidth for each bus. Further simulations were then conducted to investigate if a single data bus could accommodate all the messages and meet the latency requirement, and if so, to determine the optimum data rate on the combined bus. The results indicate that the two buses can be combined into one bus and the data rate optimized, in spite of their opposite characteristics, and still provide an adequate margin for performance. We also found that the data rate can be optimized for this application.

A robust fiber optic active star coupler for the SAE linear token-passing multiplex data bus

The Society of Automotive Engineers (SAE) linear token-passing multiplex data bus draft standard (AS4074.1, version 2.0) calls for two sets of fiber-optic medium characteristics which support a generous power loss budget of about 30 dB. Since there are applications for this bus needing an even greater loss budget one solution is to make the access coupler (the star) an active (powered) network component. A description is given of a simple, low-power, high-reliability active star coupler design meeting the overall requirements of the SAE high-speed data bus (HSDB) standard without changes to the fiber-optic implementation characteristics. The basic active star network is introduced and important quantities defined. Technical issues which influence the active star design are discussed. These include the properties of the protocol which have the greatest effect on the design of the active star, such as the initialization procedure, the system monitoring and control times, the preamble, and the intertransmission gap time. Component options are introduced and a completed design presented. Its performance in a high-speed data-bus environment is characterized and modifications to the standard for best active star performance are suggested.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>