High-speed Complementary Metal Oxide Semiconductor Research Articles

An adaptive pulse-width control loop

Clock distribution and generation circuitry forms a critical component of current synchronous digital systems. Digital system clocks must not only have low jitter and low skew, but also a well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed complementary metal oxide semiconductor (CMOS) clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital (Fenghao and Svensson 2000). In this paper, we propose a pulsewidth control loop referred as adaptive pulsewidth control loop (APWCL) that adopts the same architecture as the conventional PWCL, but with two modifications. The first one relates to implementation of the pseudo inverter control stage (PICS), while the second to involvement of adaptive control loop. The first modification provides generation of output pulses during all APWCL's modes of operation and the second faster locking time. For 1.2 μm double-metal double-poly CMOS process with Vdd = 5 V and operating frequency of 100 MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20% up to 80% if the loop parameters are properly chosen.

High-speed observations of arc modes and material erosion on RMF- and AMF-contact electrodes

Vacuum interrupters, particularly with high short-circuit interruption ability, are mostly equipped with contact systems based on two different principles: the widely used radial magnetic field (RMF) contact and the axial magnetic field (AMF) contact system. In this investigation, contact electrodes performance of an improved RMF system was compared with both an unipolar and a quadrupolar AMF contact system. By using a high-speed complementary metal oxide semiconductor digital video camera, the different systems were observed during arcing under short-circuit conditions at different current levels, concentrating on arc modes development with different arcing times. Contact erosion and thermal stress of the high-current vacuum arc on the contacts was basically evaluated on the basis of contact melting depth, with the result of comparable melting depths at insignificantly higher thermal stress of the RMF versus AMF systems. The microstructure of the copper and chromium compound contact material cross section was analyzed by means of a scanning electron microscope.

Circuit Responses to Radiation-Induced Upsets

AbstractHistorically, radiation-induced corruption of data in high-speed complementary metal oxide semiconductor designs has been limited to on-board static random-access memory in various memory caches. Successive generations of scaling, however, have resulted in capacitance reductions in key logic circuits, increasing their vulnerability to these “soft errors.” Charge delivered by radiation events now carries a substantial probability of inducing upsets, not only in bistable elements, but in logic evaluation circuits as well. This article introduces the reader to common logic-circuit topologies in high-speed microprocessors, radiation circuit response mechanisms that can compromise logic evaluation integrity, and existing techniques that mitigate this exposure.

Speed-power-accuracy tradeoff in high-speed CMOS ADCs

In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metal-oxide-semiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scaling and mismatch scaling trends are discussed and it is shown that in future technologies the power consumption of matching-dominated high-speed ADCs will increase to achieve the same accuracy and speed. Also, a comparison is made between slew-rate dominated circuits and settling dominated circuits. Finally, a comparison with published high-speed ADCs is presented using the figure of merit.

New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design

A new simple but accurate simultaneous-switching-noise (SSN) model for complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) package design was developed. Since the model is based on the sub-micron metal-oxide-semiconductor (MOS) device model, it can predict the SSN for today's sub-micron-based very large scale integration (VLSI) circuits. In order to derive the SSN model, the ground path current is determined by taking into account all the circuit components such as the transistor resistance, lead inductance, load capacitance, and oscillation frequency of the noise signal. Since the current slew rate is not constant during the device switching, a rigorous analysis to determine the current slew rate was performed. Then a new simple but accurate closed-form SSN model was developed by accurately determining current slew rate for SSN with the alpha-power-law of a sub-micron transistor drain current. The derived SSN model implicitly includes all the critical circuit performance and package parameters. The model is verified with the general-purpose circuit simulator, HSPICE. The model shows an excellent agreement with simulation even in the worst case (i.e., within a 10% margin of error but normally within a 5% margin of error). A package design methodology is presented by using the developed model.

High-speed CMOS switch designs for free-space optoelectronic MIN's

We present the theory, experimental results, and analytical modeling of high-speed complementary metal-oxide-semiconductor (CMOS) switches, with a two-dimensional (2-D) layout, suitable for the implementation of packet-switched free-space optoelectronic multistage interconnection networks (MIN's). These switches are fully connected, bidirectional, and scaleable. The design is based on the implementation of a half-switch, which is a two-to-one multiplexer, using a 2-D layout. It introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5 V being the third value for a 5 V power supply. Simulations show that for a 0.8-/spl mu/m CMOS technology the switches can operate at speeds up to 250 Mb/s. Scaled-down versions of the switches have been successfully implemented in 2.0 /spl mu/m CMOS. The analytical modeling of these switches show that large scale free-space optoelectronic MIN's using this concept could offer close to Terabit/sec throughput capabilities for very reasonable power and area figures. For example, a 4096 channel system could offer 256 Gb/s aggregate throughput for a total silicon area of about 18 cm/sup 2/ and a total power consumption (optics plus electronics) of about 90 W.

Picosecond hot electron light emission from submicron complementary metal–oxide–semiconductor circuits

Optical emission consisting of pulses with temporal widths of less than 270 ps has been detected from fully functional silicon integrated circuits fabricated using submicron complementary metal– oxide–semiconductor (CMOS) logic gates. Emission is observed under normal bias conditions and occurs when the gates are switching. The emission arises from the hot electron populations created by the transient current pulses present in the transistors during switching. The speed and spectral characteristics of the emission suggest future applications in the measurement of timing in high speed CMOS circuits.

21-ps 0.1- mu m CMOS devices operating at room temperature

High-speed complementary metal-oxide semiconductor (CMOS)-inverter ring oscillators with the shortest gate length of 0.17 mu m were fabricated by a conventional large-scale integrated (LSI) technology. The propagation delays were 21 ps / stage (2.0 V) at room temperature and 17 ps / stage (2.0 V) at 80 K. These results are the fastest records reported for bulk CMOS devices as of today. The results were obtained by reducing effective drain junction capacitances with "double-finger gates," and devices will probably be faster if the areas are completely proportionally reduced to the feature size. Though it is important for CMOS devices to increase drain currents, a silicidation technique for source and drain was not necessary for the tested devices to reduce series resistance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The design of the 88000 RISC family

The design and implementation of the RISC (reduced-instruction-set computer) 88000 system in high-speed, complementary metal-oxide semiconductor (HCMOS) technology is described. The total system consists of the 88100 processor and two 88200 cache memory management units (CMMUs). The various features and components of the 88000 are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>