High-speed Comparator Research Articles

Design and Analysis of High Gain Low Power CMOS Comparator

The comparator is the most significant component of the analog-to-digital converter, voltage regulator, switching circuits, communication blocks etc. Depending on the various design schemes, comparator performance varied upon target applications. At present, low power, high gain, area efficient and high-speed comparator designed methods are necessary for complementary metal oxide semiconductor (CMOS) industry. In this research, a low power and high gain CMOS comparator are presented which utilized two-stage differential input stages with replication of DC current source to achieve higher gain, higher phase margin, higher bandwidth, and lower power consumption. The simulated results showed that, by using a minimum power supply of 1.2 V, the comparator could generate higher gain 77.45 dB with a phase margin of 60.08°. Moreover, the modified design consumed only 2.84 µW of power with a gain bandwidth of 30.975 MHz. In addition, the chip layout area of the modified comparator is found only 0.0033 mm 2 .

Comparator hysteresis compensation for decision feedback equalisers

High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations.

A Low-Power High-Speed Comparator for Precise Applications

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$ . The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz.

A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits

A new leakage tolerant high speed domino gate having higher noise immunity, low power dissipation, and less process variations for wide fan-in OR logic is developed. This paper deals with the design of a high speed comparator based domino gate with low leakage that decides the output on the basis of voltage difference across the pull down network. In order to design mirror of voltage comparator, PMOS is replaced by NMOS for low process variation. Furthermore, stacking of NMOS is accomplished to reduce leakage and total current transfer in cascode fashion. Hence, the proposed domino can be operated in deep submicron regime. The simulation results confirm that the proposed domino gate exhibits about 17.58% power dissipation reduction and 1.21 times noise immunity improvement in contrast with reported voltage comparison based domino. The simulation results are achieved with Cadence Virtuoso environment using SPECTRE simulator in 45 nm CMOS technology.

A 0.18-μm CMOS high-data-rate true random bit generator through ΔΣ modulation of chaotic jerk circuit signals.

A full-custom design of chaos-based True Random-Bit Generator (TRBG) implemented on a 0.18-μm CMOS technology is presented with unique composition of three major components, i.e., (i) chaotic jerk oscillator, (ii) ΔΣ modulator, and (iii) simple pre/post-processing. A chaotic jerk oscillator is a deterministic source of randomness that potentially offers robust and highly random chaotic signals and exhibits a distinctive property of smoothly balanced-to-unbalanced alternation of double-scroll attractors. The continuous-time 2nd-order ΔΣ modulator is introduced as a mixed-signal interface in order to increase a resolution of random bit sequences while no extra clock is required. The ΔΣ modulator is constructed mainly by a folded-cascode amplifier with sufficient gain and phase margin of 64 dB and 83°, respectively, and a high-speed comparator with a time constant of 2.7 ns. An uncomplicated structure of shift-registers is realized as a post-processing process. The bit sequence of the proposed TRBG successfully passes all statistical tests of NIST SP800-22 test suite, and the ultimate output bit rate is 50 Mbps. The physical layout of a chip area is 212.8 × 177.11 μm and the DC power dissipation is 1.32mW using a 1.8-V single supply voltage. This paper therefore offers a potential alternative to a fully embedded cryptographic module in ASIC applications.

40 Gbps 4‐level pulse amplitude modulation closed‐loop decision‐feedback equaliser with high‐speed comparator in 55 nm CMOS technology

A 40 Gbps 4-tap 4-level pulse amplitude modulation closed-loop decision feedback equaliser (DFE) is proposed. The DFE adopts a novel high-speed comparator to resolve the critical timing constraints of the first tap. The comparator decreases the slicing delay by shortening the gap between initial and target voltages. Compared with the existing closed-loop DFE designs, the proposed scheme relieves timing constraints without complex clock distribution circuits and extra area. Simulations based on the RF-MOS model verify that the delay of the comparator is improved by 32.8% and the output swing is increased by more than 2.8 times. The proposed DFE which can compensate −9.5 dB channel loss is designed in 55 nm CMOS technology. The power consumption is 67 mW from a 1.2 V supply and the circuit occupies an active area of 0.021 mm2, achieving 1.68 pJ/bit energy efficiency.

Design of a Low Power and High Speed Comparator using Mux based Full Adder Cell for Mobile Communications

Design of a Low Power and High Speed Comparator using Mux based Full Adder Cell for Mobile Communications

UHF PD measurement system with scanning and comparing method

Based on the periodic and repetitive characteristics of partial discharge (PD) under power frequency voltage, an ultra-high-frequency (UHF) PD measurement system using scanning and comparing method is realized without analog to digital (A/D) acquisition. The UHF PD pulses are compared with adjustable reference levels by high-speed comparator, and the number of pulses higher than the reference levels is recorded by a field programmable gate array (FPGA) along with corresponding phase information. The phases, amplitudes and number of discharge pulses can be extracted from the acquired data, which is verified in needle-plate PD experiment result analysis. And PD spectrograms of proposed method proves to be highly correlated with that of pulse current method and conditional UHF method. Influence factors in PD signal acquisition process are also analyzed.

A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS

We present a single-channel 10-b 400-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) embodying a proposed 2-b/step conversion scheme with single reference voltage for the IEEE 802.11ac. By means of the said scheme, the proposed ADC requires only three capacitor arrays instead of at least four capacitor arrays in other capacitor digital-to-analog converter-based 2-b/step SAR ADCs. The proposed ADC features a small input capacitance loading, thereby alleviating the driving requirement of the power-hungry input buffer in the IEEE 802.11ac system; and features a symmetrical architecture with highly matched interconnections. In addition, the proposed ADC embodies a proposed high-speed dynamic comparator with kickback noise cancelation and high-speed successive approximation (SA) control logic for high conversion rate and resolution. The proposed ADC prototype fabricated in 65-nm CMOS process achieves signal-to-noise-and-distortion-ratio >52 dB across 200-MHz Nyquist bandwidth, while dissipating 5.61-mW power. The ADC prototype, when benchmarked with state-of-the-art 2-b/step SAR ADCs, features a highly competitive figure-of-merit, i.e., 43 fJ/conv.step.

A high speed photon counter system for microwave mercury ion frequency standard

This report describes a high speed photon counter system for microwave mercury ion frequency standard based on a field programmable gate array (FPGA). A high speed comparator is chosen to convert analog signal to digital pulse. A circuit with low-voltage differential signaling (LVDS) receiver in FPGA is used to capture the rising edges of the pulses. In our experiment, the clock of the Altera FPGA EP4CE10E22C8N is 80 MHz which is easy for logic design, and the de-serialization factor of the LVDS receiver is 8, the measured minimum pulse width that can be correctly captured is about 1.67 ns. As a compact and low-cost module, the photon counter system is used for the microwave mercury ion frequency standard.

Agile All-Digital RF Transceiver Implemented in FPGA

This paper presents a new all-digital transceiver architecture fully integrated into a single field-programmable gate array chip. Both the radio frequency (RF) receiver and the transmitter were entirely implemented using a digital datapath from the baseband up to the RF stage without the use of conventional analog-to-digital converter, digital-to-analog converter, or analog mixer. The transmitter chain uses delta-sigma modulation and digital upconversion to produce a two-level RF output signal. The receiver uses a high-speed comparator and pulsewidth modulation to convert the RF signal into a single-bit data stream, which is digitally filtered and then downconverted. Both the transmitter and the receiver are agile with flexible carrier frequency, bandwidth, and modulation capabilities. The transceiver error vector magnitude and the signal-to-noise ratio figures of merit were analyzed in a point-to-point transmission to evaluate the transmitter’s performance. The results show the feasibility of this approach as a more flexible alternative to common radio architectures.

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.

A Design of a 92.4% Efficiency Triple Mode Control DC–DC Buck Converter With Low Power Retention Mode and Adaptive Zero Current Detector for IoT/Wearable Applications

This paper presents a retention/ pulse frequency modulation (PFM)/ pulse width modulation (PWM) mode dc–dc buck converter with adaptive zero current detector (AZCD) and spread spectrum clock generation (SSCG) for IoT/Wearable systems. The proposed dc–dc buck converter is capable of handling loads from 10 μA to 20 mA with high efficiency by applying triple mode (retention mode, PFM mode, and PWM mode), gate split technique, and AZCD. Retention mode is proposed to extend wide load range at ultralight load. Gate split technique adjusts the conduction loss and switching loss. AZCD reduces the operation duty of the high-speed comparator and avoid reverse current below light load. In IoT applications, each node communicates with other nodes through a Bluetooth low energy transceiver, which consumes very low current and is highly sensitive to supply noise. Therefore, the proposed dc–dc buck converter adopts the SSCG technique to reduce electromagnetic interference by up to 18 dB. This chip is implemented using 0.13 μm CMOS technology with an active area of $\text{820}\times \text{800}\;\mu \text{m}^{2}$ . The maximum power efficiency of the proposed dc–dc buck converter is 92.4% at a switching frequency of 2.5 MHz when the load current range is 10 to 20 mA. The input voltage range and the regulated output voltage are 2.2–3.3 and 1.7 V, respectively. In addition, the proposed dc–dc buck converter achieves over 74.2% efficiency in retention mode when the load current range is from 10 to 500 μA.

A new high-speed low-power and low-offset dynamic comparator with a current-mode offset compensation technique

In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of the latch stage significantly reduces the delay time of the latch and relaxes the need for high current in the regeneration process which ensures low-power structure. In addition, a new digitally controlled offset cancellation circuit based on the current-steering structure is used to reduce the offset of comparator. Offset voltage reduction in the startup time is the key advantage of the proposed calibration technique which does not require refreshing the offset cancellation process. Post-layout simulation results in 0.18µm standard TSMC CMOS process show that the designed comparator dissipates 135µW of power consumption from a 1.2V supply voltage and has the 1mV accuracy while operating at 1GHz clock frequency. The power and delay time of the proposed comparator are less than about 10% of the new state-of-the-art comparator. Furthermore, from the Monte-Carlo analysis, the standard deviation of the input referred offset voltage in typical process corner and temperature is obtained about 17.53/1.09mV before and after offset cancellation, respectively.

A 30-W 90% Efficiency Dual-Mode Controlled DC–DC Controller With Power Over Ethernet Interface for Power Device

A dual-mode controlled dc–dc controller with power over Ethernet (PoE) interface for power device (PD) is presented that is designed to support drawing power either from an Ethernet cable or from an external auxiliary supply support (ASS). PoE interface supports all the functions that comply with the IEEE802.3af/at standard. Based on bandgap reference structure, a detection comparator is provided to detect input voltage without extra voltage reference. Using a low offset voltage amplifier, a low-loss current-limiting technique is proposed to achieve a high-precision current-limit point. Based on a high-speed comparator and two timing capacitors, an oscillator (OSC) is implemented for better accuracy, and provides the maximum duty cycle ( $D_{\mathrm {max}}$ ) and external frequency synchronization. The chip is fabricated in a 0.5- $\mu \text{m}$ 65 V BCD process and occupies a die size (with pads) of $1.79 \times 2.76$ mm2. The experimental results are measured for an active clamp forward converter with a wide range of dc input voltages from 33 to 57 V, an output voltage of 12 V, and an output power of 30 W. The chip achieves peak power efficiency of 90% and 90.63% on DC and ASS, respectively. The load regulation at different input voltages can be measured to be within ±0.11%. Measurements further show that the peak-to-peak ripple voltage of the chip is 161 mV and the recovery time is less than 1.2 ms for the 2-A load step.

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13μm technology with the supply voltage of 1V.

Improved double noise coupling ΔΣ analog-to-digital converter

In Jung et al. (Electron Lett 48(10):557---558, 1), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference, 2). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly.

A Simple Control Strategy Using Speedy Transient Response for Multiphase Buck Converter

The high performance of recent originating digital processors requires power supply for transient output, firm voltage regulation and high current. Industry has taken up interleaved multiphase synchronous buck converters for meeting such demands. Application of the voltage mode (ripple) hysteretic strategy to multiphase Voltage Regulator Units (VRU) would help satisfying many of the upcoming digital processors and IC’s powering demands. This arises from the use of the various advantages that can be obtained from this technique. This current division method is known for several benefits it provides: easy accessibility in application to all control methods, with freedom from the prime control technique in voltage regulation loop, absence of any necessity for current reference, better accuracy in current division of equal magnitude at almost every load conditions in standstill and transients. As against this, there are several challenges that involve distribution of multiple control signals, current sharing and sensitivity to noise, high speed comparators, hysteretic band accuracy and stable at large load transients. In addition, application of the current division technique presented was made to a multiphase voltage mode ripple controlled Buck Converter that produced a novel and easy control strategy having minimum output voltage ripples and speedy transient output.

Single‐stage AC–DC voltage regulator for 15 W wireless charging

A single-stage AC–DC voltage regulator is proposed to enhance the power efficiency while at the same time reducing the design complicity of the entire system. Unlike the traditional two-stage AC–DC regulator, a pulse-width modulation control algorithm is integrated to switch the working mode of an active rectifier between a charging mode and a zero mode to maintain the output voltage at 5 V. This in turn efficiently eliminates the need for a DC–DC converter following the rectifier. Besides, a coupled full-bridge active rectifier with high speed comparator dramatically reduces the power loss of the circuit. Experiment results using a 0.35 µm technology and a PCB circuit demonstrate the advantages of the proposed design.

Design and Simulation of Low Power and High Speed Comparator using VLSI Technique

Design and Simulation of Low Power and High Speed Comparator using VLSI Technique