High-speed CMOS Image Sensor Research Articles

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor.

To reduce the power consumption of a TDC in high-speed applications, a TDC architecture applied to SS ADC is proposed to reduce redundant counting. This structure can remove the identical part between two rows of pixel signals in a CMOS image sensor by adjusting the start and stop signal of the TDC, which will reduce the number of flipping of D flip-flops in the TDC. This structure requires the simultaneous readout of two rows of pixels in the high-speed CMOS image sensor. In the 110 nm CMOS process, simulation results show that the designed 5-bit TDC achieves an effective number of bits (ENOB) at 4.72 bits and a figure-of-merit (FOM) at 104.7-162.3 fJ/step, with a power consumption ranging from 60 µW to 93 µW. Compared with traditional counting methods, the proposed TDC can reduce counting power consumption by 30%.

A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors

This paper proposes a 13-bit two-step single-slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional method's time redundancy issue. The differential nonlinearity (DNL) and integral nonlinearity (INL) are simulated to be +0.8/-0.8 LSB and +2.1/-3.5 LSB, respectively, for the 55 nm 1P4M CMOS process. 512 ns is the conversion time of the 13-bit ADC. The power consumption is 47 μW, and the effective number of bits (ENOB) is 11.33 bits. In comparison to existing advanced ADCs, the method proposed in this paper can increase the ADC conversion rate by more than 60% while maintaining low power consumption and high precision, thereby providing theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.

2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout technique is proposed, which optimizes the quantization method. And the proposed SS ADC prioritizes the quantization of the most significant bit (MSB), aiming to shorten the search range of the slope and greatly improve the quantization speed while ensuring accuracy. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed SS ADC is designed and simulated with 0.11-μm process. The simulation results show that the row time of SS ADC is 2 μs and the resolution is 500 ps, which greatly improves the quantization speed while ensuring power consumption and accuracy. The FoM is 182.6 fJ/step, which is a 7.1% improvement compared to other TDC-based SS ADCs. The proposed SS ADC becomes more effective as the bit-depth of the ADC increases.

Study on the performance of high-speed CMOS image sensors in transient imaging mode

Study on the performance of high-speed CMOS image sensors in transient imaging mode

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/−0.8 LSB and the integral nonlinearity (INL) of +1.06/−0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of $7.5\times 775\,\,\mu \text{m}^{2}$ and the power consumption is $72~\mu \text{W}$ .

PETAL: A Multichannel Differential ADC Driver for High-Speed CMOS Image Sensors

Programmable Electronic Termination and Line Driver (PETAL) is a 16-channel ADC driver chip that provides single-ended-to-differential conversion and column biasing for high-speed CMOS image sensors. By increasing the level of integration, the number of driver chips and the associated number of passives and the routing area are reduced, enabling smaller physical cameras. Power dissipation is reduced relative to many commercial approaches by the use of low-voltage CMOS technology and the increased level of integration. The driver chip also supplies programmable bias currents to the sensor, further reducing the number of required components on the camera board. The driver, fabricated in 180-nm CMOS technology, achieves settling to 0.1% in 11 ns with input noise of 89.9- $\mu \text{V}$ rms. The crosstalk between channels is below −56 dB. The power dissipation is 10.5 mW/channel. When applied to the readout of a high-speed X-ray sensor, the prototype reduced board area by 84% (from 100 to 16 mm2) and power dissipation by 25%.

Design of Novel Pixel with Non-Uniform Doped Transistor Channel and Triangle-Tooth Shape Pinned Photodiode for High Speed CMOS Image Sensors

Design of Novel Pixel with Non-Uniform Doped Transistor Channel and Triangle-Tooth Shape Pinned Photodiode for High Speed CMOS Image Sensors

A fast correlated multiple sampling technique based on 12-bit SAR ADC with digital calibration for low-noise CMOS image sensor

A fast multiple correlated sampling technique based on successive approximation register analog-to-digital converter (SAR ADC) for low-noise CMOS image sensors is proposed in this paper. During the whole operation of the fast multiple correlated sampling, m-times samplings and conversions are achieved. The SAR ADC completes a full conversion in the first conversion and only converts lower M bits in the following conversions to decrease the total conversion time. The influences of three factors, the number of samplings, the number of bits converted in the repeated conversions and the resolution of ADC, on the fast multiple correlated sampling are analyzed in detail. A 12-bit SAR ADC with digital calibration based one bit redundancy to relieve the requirement of the capacitor mismatch is designed in the fast correlated multiple sampling technique. The proposed correlated multiple sampling technique is implemented and simulated through standard 180nm CMOS process. The SAR ADC achieves 72.55dB signal-to-noise-and-distortion ratio after digital calibration. The simulation results match the analysis well. Readout noise in CMOS image sensors can be reduced by the factor of m effectively with appropriate M based on the fast correlated multiple sampling technique. The total conversion time is decreased effectively, and it is only 10.9μs for 16 times fast correlated multiple sampling. The fast multiple correlated sampling technique based on SAR ADC is suitable for low-noise and high-speed CMOS image sensor.

A High-speed Low-power CMOS Image Sensor with Delta and Interpolation Readout Scheme

A High-speed Low-power CMOS Image Sensor with Delta and Interpolation Readout Scheme

3. Recent Technology Trend of ADCs for High Speed CMOS Image Sensors

3. Recent Technology Trend of ADCs for High Speed CMOS Image Sensors

A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18μm CMOS process. The measurement results show that the random noise (RN) is 7erms−, the pixel conversion gain is 100μV/e−. Since the measured full well capacity of the pixel is 25000e−, the CMOS image sensor achieves a 71dB dynamic range (DR). The total power consumption at 60frame/s is 58.2mW.

A 10-Bit Column-Parallel Single Slope ADC Based on Two-Step TDC with Error Calibration for CMOS Image Sensors

This paper presents a 10-bit column-parallel single slope analog-to-digital converter (SS ADC) with a two-step time-to-digital converter (TDC) to overcome the long conversion time problem in conventional SS ADC for high-speed CMOS image sensors (CIS). The time interval proportional to the input signal is generated by a ramp generator and a comparator, which is digitized by a two-step TDC consisting of coarse and fine conversions to achieve a high-precision time-interval measurement. To mitigate the impact of propagation delay mismatch, a calibration circuit is also proposed to calibrate the delay skew within -T/2 to T/2. The proposed ADC is designed in 0.18 μm CMOS process. The power dissipation of each column circuit is 232 μW at supply voltages of 3.3 V for the analog circuits and 1.8 V for the digital blocks. The post simulation results indicate that the ADC achieves a SNDR of 60.89 dB (9.82 ENOB) and a SFDR of 79.98 dB at a conversion rate of 2 MS/s after calibration, while the SNDR and SFDR are limited to 41.52 dB and 67.64 dB, respectively before calibration. The differential nonlinearity (DNL) and integral nonlinearity (INL) without calibration are +15.80/-15.29 LSB and +1.68/-15.34 LSB while they are reduced down to +0.75/-0.25 LSB and +0.76/-0.78 LSB with the proposed calibration.

A high speed CMOS image sensor with a novel digital correlated double sampling and a differential difference amplifier.

In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.

A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor

A low power 8T global shutter pixel with extended FD voltage swing range is proposed for large format high speed CMOS image sensor. The pixel has a negative threshold reset transistor, two in-pixel source followers, and a sample-and-hold circuit. The in-pixel first source follower is employed for reducing the pixel average current and maximum transient current. The negative threshold reset transistor is applied to extend the voltage swing of FD. Using pixel level sample-and-hold circuit, the kTC noise on FD node can be effectively nullified by correlated double sampling operation. A high speed 1000 fps 256×256 CMOS image sensor is implemented in 0.18 μm CMOS process. Two 10-bit cyclic ADC arrays are integrated in this prototype sensor chip. The active area of the chip is 10 mm×7 mm with a pixel size of 14 μm×14 μm. The developed sensor achieves an average current of 23 nA per pixel, a maximum transit current per pixel as low as 1113 nA, and a large FD voltage swing of 1.78 V. The sensor temporal noise level is 103 e- and full well capacity has 27000 e- which results in 48.3 dB signal dynamic range.

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

Process techniques of charge transfer time reduction for high speed CMOS image sensors

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 × 64 pixels was designed and implemented in the 0.18 μm CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.

A reconfigurable 256 × 256 image sensor controller that is compatible for depth measurement

This paper presents an image sensor controller that is compatible for depth measurement, which is based on the continuous-wave modulation time-of-flight technology. The image sensor controller is utilized to generate reconfigurable control signals for a 256 × 256 high speed CMOS image sensor with a conventional image sensing mode and a depth measurement mode. The image sensor controller generates control signals for the pixel array to realize the rolling exposure and the correlated double sampling functions. An refined circuit design technique in the logic level is presented to reduce chip area and power consumption. The chip, with a size of 700 × 3380 μm2, is fabricated in a standard 0.18 μm CMOS image sensor process. The power consumption estimated by the synthesis tool is 65 mW under a 1.8 V supply voltage and a 100 MHz clock frequency. Our test results show that the image sensor controller functions properly.

A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

This paper presents a 12-bit column-parallel successive approximation register analog-to-digital converter (SAR ADC) for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital-to-analog converter (CDAC) and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020 μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/−1 LSB, 1/−1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-V supply and decreases linearly as the frame rate decreases.

Piecewise Linear Response Based on CMV4000 Image Sensor

With high speed CMOS image sensor CMV4000 produced by CMOSIS company as the object, after the thorough analysis of the piecewise linear response principle and how to extend the dynamic range, using piecewise linear response extends the dynamic range of CMV4000 image sensor. The ideas and methods of using the finite state machine designs piecewise linear response sequence are given, and the function simulation is done for the sequence in the Quartus II 9.0 environment using the Verilog HDL hardware description language. Through the analysis of simulation results, it can satisfy the demands of piecewise linear response sequence. The method is simple and feasible, and can improve the optical dynamic range of CMV4000 image sensor.

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.