High-speed Clock Research Articles

A novel frequency discriminated phase controller for high-speed optical clocks generated from laser diodes

We demonstrate the in-situ frequency discrimination and continuous phase tuning of high-speed optical clocks generated from a directly modulated/encoded laser diode with respect to a free-running microwave clock. This is performed by using a DC-voltage controlled, frequency-discriminated optoelectronic phase shifter (OEPS). The transfer function of the phase shifter versus controlled voltage is linear with a maximum phase-tuning range of up to 1.957/spl pi/ (340/spl deg/). The tuning responsivity of the OEPS can be adjusted from 50 to 90/spl deg//V. The fluctuation and drift in phase of the controlled signal are about 0.05/spl deg/ and 0.003/spl deg//min. The tuning resolution of 0.2/spl deg/ at a 3-mV increment of controlling voltage is achieved by using a high-precision voltage regulator. Relative timing jitter of the controlled optical microwave clock is less than 5 ps.

Exploiting the on-chip inductance in high-speed clock distribution networks

On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits.

Impact of small process geometries on microarchitectures in systems on a chip

Process effects in deep-submicrometer geometries are expected to change the physical organization, or microarchitecture, of integrated circuits. The factor that is expected to primarily impact integrated circuit microarchitectures is increasing delays in interconnect. We believe that, to properly microarchitect integrated circuits in small process geometries, it is necessary to get as detailed a picture as possible of the effects and then to draw conclusions about changes in microarchitecture. To this end, in this paper we describe a comprehensive approach to accurately characterizing the device and interconnect characteristics of present and future process generations. This approach uses a detailed extrapolation of future process technologies to obtain a realistic view of the future of circuit design. We then proceed to quantify the precise impact of interconnect, including dynamic delay due to noise, on the performance of high-end integrated circuit designs. Having determined this, we then reconsider the impact of future processes on integrated-circuit design methodology. We determine that local interconnect effects can be managed through a deep-submicrometer design hierarchy that uses 50 K-100 K gate modules as primitive building blocks. In light of this new system-on-a-chip microarchitecture, we then examine global interconnect issues. Our results indicate that, while global communication speeds will necessarily be lower than local clock speeds, international Technology Roadmap for Semiconductors expectations should be attainable to the 0.05-/spl mu/m technology generation. Achieving these high clock speeds (10 GHz local clock) will be aided by the use of a newly proposed routing hierarchy that limits interconnect effects at each level of a design (local, isochronous, and global). In addition, key components of the interconnect architecture of the future include fat (or unscaled) global wires, intelligent repeater and shield wire insertion, and efficient packaging technologies.

Design and analysis of a portable high-speed clock generator

A new portable clock generator with full pull-in range and fast acquisition is presented in this paper, where it can be developed at hardware description language (HDL) to reduce design cycle as well as improve system-level integration simulation. In the proposed design, frequency tracking is performed by the Prune-and-Search algorithm, and the digital-controlled ring oscillator is constructed by CMOS standard cells. In order to reduce propagation delay of the loop divider, a novel structure is developed to provide a constant delay at any divider setting. In addition, input jitter can be isolated to avoid coupling by digital processing. Hence, the generated clock output becomes more clean and robust. Based on the proposed methodology, a test chip has been designed and verified on 0.6-/spl mu/m CMOS process with frequency range of (360 /spl sim/ 800) MHz at 3.3 V and peak-to-peak jitter of less than 60 ps at 800 MHz/3.3 V.

50 GHz RSFQ pseudo-random number generator design

Simple RSFQ gates can be very robust, and operate up to high clock speeds in simulation. Larger RSFQ circuits are generally much more limited in clock speed. We believe that this is partly due to less than optimal choice of the timing inter-connections between gates. Timing design is especially problematic for circuits including data loops (feedback). We have developed a new technique for timing design of RSFQ data loops which may be called "balanced skew clock scheduling." It involves equalizing the minimum clock period between every pair of gates. Mathematical analysis proves the optimality of this scheme and reveals the global timing constraints unique to RSFQ data loops. We used this technique for the design of a simple useful clocked RSFQ circuit, a four-bit pseudo-random number generator (PRNG). Constructed from our standard library cells for a 3.5 /spl mu/m 1000 A/cm/sup 2/ Nb-trilayer process, the PRNG worked up to 50 GHz in Jspice simulation.

Analysis of electromagnetic coupling effects in integrated Josephson junction logic devices by the FDTD technique

A very important step of the design of circuits and devices in the Josephson junction technology is the complete and correct calculation of their electrical characteristics. Due to the very high clock speed of up to 100 GHz, dynamic effects like the electromagnetic coupling start to play a significant role over the operation of the system. The presented work reports on the implementation of the FDTD technique for the description of the electromagnetic coupling effects in the Josephson devices. Some typical microstrip layouts are considered strictly taking in account the technological specifications. The obtained results are analyzed in respect to the constraints, which the coupling effects impose on the lateral dimensions of the microstrip lines.

High Speed Clock Design beyond 1 GHz Frequency.

High Speed Clock Design beyond 1 GHz Frequency.

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which promotes evolution. A net child chromosome generation rate of one per clock cycle is obtained by pipelining the parent selection, crossover, mutation, and fitness evaluation functions. Complex fitness functions can be further pipelined to maintain a high-speed clock cycle. Fitness functions with a pipeline initiation interval of greater than one can be plurally implemented to maintain a net evaluated-chromosome throughput of one per clock cycle. Two prototypes are described: The first prototype (c. 1996 technology) is a multiple-FPGA chip implementation, running at a 1 MHz clock rate, that solves a 94-row × 520-column set covering problem 2,200× faster than a 100 MHz workstation running the same algorithm in C. The second prototype (Xilinx XVC300) is a single-FPGA chip implementation, running at a 66 MHZ clock rate, that solves a 36-residue protein folding problem in a 2-d lattice 320× faster than a 366 MHz Pentium II. The current largest FPGA (Xilinx XCV3200E) has circuitry available for the implementation of 30 fitness function units which would yield an acceleration of 9,600× for the 36-residue protein folding problem.

A digital implementation of a frequency steered phase locked loop

A digital implementation of a new technique that delivers an extremely accurate and stable phase locked loop system (PLL) is presented. The new technique uses competing phase and frequency loops to incorporate an accurate local reference frequency into the phase locked loop structure. Disturbances on the phase loop caused by the digital frequency loop are identified and a method to mitigate the disturbances is developed. The implementation is primarily designed for high-speed clock and data recovery and experimental results from a clock recovery system for nonreturn to zero data streams at 155.52 MHz are presented.

Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications

This paper describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. Fully differential CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system, although the design can be used in other systems with clock speeds in the 622-933-MHz range. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a differential charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. Two test chips are implemented in 0.35-/spl mu/m CMOS. One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external loop filter, can be used for flexible testing and CDR applications. The other chip is a monolithic CDR with integrated loop filter. It exhibits a power consumption of 0.2 W and a measured rms clock jitter of 12.5 ps at 933 MHz.

An asynchronous protocol for virtual factory simulation on shared memory multiprocessor systems

The development of parallel simulation technology is seen as an enabler for the implementation of the virtual factory concept, the integrated simulation of all the systems in a factory. One important parallel simulation protocol, the asynchronous deadlock avoidance algorithm proposed by Chandy, Misra, and Bryant, has usually been discussed in the context of distributed memory systems. Also, null messages have normally been associated with this approach for deadlock avoidance. This paper presents a new implementation of the CMB protocol designed for shared memory multiprocessor systems. We have successfully used this protocol, which we call the CMB-SMP protocol, to achieve useful speedups in a manufacturing simulation application, despite the fine granularity of event processing. The implementation eliminates the need for sending null messages, without causing deadlock in the simulation. Double buffering is also used to reduce the overhead of buffer locking. It is shown that the CMB-SMP protocol outperforms a synchronous super-step protocol in terms of the speedups achieved. The paper also discusses the cache behaviour of the CMB-SMP protocol implementation since cache misses are very expensive with today's high clock speed processors.

Pulsewidth control loop in high-speed CMOS clock buffers

In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital. Signal quality degradation is influenced by temperature and process deviation. In this paper, we propose a pulsewidth control loop to get required pulsewidth. To investigate the loop stability, a linearized small signal analysis model is used. Results of SPICE simulation show that the pulsewidth can be well controlled if the loop parameters are properly chosen. The pulsewidth can be easily adjusted to a desired value by sizing the ratio of transistor sizes in the current mirror of charge pump.

FPGA-based SAT solver architecture with near-zero synthesis and layout overhead

Boolean satisfiability (SAT) has shown itself to be a promising application for configurable computing and an interesting testbed for new configurable computing compilation techniques. In this paper we have developed a new and novel SAT solver architecture that addresses three fundamental hurdles that remain before reconfigurable-hardware-based acceleration of SAT can be widely used. These hurdles are: first, the time overhead for compiling the instance-specific circuit to hardware; secondly, the limited sophistication of the hardware algorithm, and thirdly, the slow clock speeds. The main enabling idea in our work is to implement the communication between literals and clauses by means of a time multiplexed pipelined bus architecture rather than hardwiring it using on-FPGA routing resources. This allows the circuits for different instances of the SAT problem to be identical except for small local differences. Thus, the incremental synthesis and place-and-route effort required for each instance of the problem becomes negligible compared to the time to actually solve the SAT problem. Interestingly, the time multiplexing feature also allows us to incorporate the dynamic addition of clauses into the SAT solver algorithm, since the compilation/configuration time is negligible. Finally, since the proposed architecture is highly pipelined, with very few long wires, and no wires crossing FPGA boundaries, high clock speeds are possible. The authors present the overall architecture and detailed circuits for it in the paper. They also present experimental results showing the performance of the architecture relative to earlier efforts on hardware acceleration of SAT and relative to software implementations.

A global wiring paradigm for deep submicron design

Global interconnect is commonly regarded as a key potential bottleneck to the advancing performance of high-speed integrated circuits. Our previous work has suggested that local interconnect effects can be managed through a deep submicron design hierarchy that uses 50000 to 100000 gate modules as primitive building blocks. The primary goal of this paper is to examine global interconnect effects, within such a design hierarchy, to determine if there are any significant roadblocks which will prevent National Technology Roadmap for Semiconductors (NTRS) performance expectations from being met. Specifically, the issues of global resistance-capacitance delay, signal time-of-flight, inductance, clock and power distribution, and noise are studied. Results indicate that, while global clock frequencies will necessarily he lower than local clock speeds, NTRS expectations should be attainable to the 50 nm technology generation. Achieving these high clock speeds (10 GHz local clock) will be aided by the use of a newly proposed routing hierarchy which limits interconnect effects at each level of a design (local, isochronous, and global).

Runtime reconfiguration techniques for efficient general-purpose computation

By exploiting hardware partitioning and applying runtime reconfiguration techniques, microprocessor efficiency is significantly improved while retaining high clock speed, dense functionality, and conventional development tools.

Improved VLSI interconnect

Metal interconnect has become a major limiting factor in the growth of VLSI technology. A passive VLSI interconnect layout is proposed in which the current density is constant along its length. The result is a tapered track that has lower capacitance, hence lower power consumption, and improved high frequency performance. Simulations indicate that tapered tracks give delay reductions that permit operating frequencies up to 33% higher, and power savings of 42%, compared with equivalent rectangular tracks. Such interconnects will be of value in high speed clock nets where low skew and long paths are necessary.

A 60-GHz f/sub T/ super self-aligned selectively grown SiGe-base (SSSB) bipolar transistor with trench isolation fabricated on SOI substrate and its application to 20-Gb/s optical transmitter ICs

A 60-GHz cutoff frequency (f/sub T/) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance C/sub CS/. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-/spl mu/m wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency f/sub T/ and the maximum frequency of oscillation f/sub max/ were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s.

Timing constraints for high-speed counterflow-clocked pipelining

With the escalation of clock frequencies and the increasing ratio of wire-to gate-delays, clock skew is a major problem to be overcome in tomorrow's high-speed very large scale integration (VLSI) chips. Also, with an increasing number of stages switching simultaneously comes the problem of higher peak power consumption. In our prior work, we have proposed a novel scheme called counterflow-clocked (C/sup 2/) pipelining to combat these problems, and discussed methods for composing C/sup 2/ pipelined stages. In this paper, we analyze in great detail the timing constraints to be obeyed in designing basic C/sup 2/ pipelined stages, as well as in composing C/sup 2/ pipelined stages. C/sup 2/ pipelining is well suited for systems that exhibit mostly unidirectional data flows as well as possess mostly nearest neighbor connections. C/sup 2/ pipelining eases the distribution of high-speed clocks, shortens the clock period by eliminating global clock signals, allows natural use of level-sensitive dynamic latches, and generates less internal switching noises due to the uniformly distributed latch operation. By applying C/sup 2/ pipelining and its composition methods to build a system, VLSI designers can substitute the global clock-skew problem with many local one-sided delay constraints.

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface

A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using (1) a rotated hierarchical I/O architecture to reduce power noise and to minimize the chip-size penalty associated with an 8-bit prefetch architecture implemented with 16 internal banks and 144 I/O lines, (2) a delay-locked-loop circuit using a high-speed and small-swing differential clock to achieve the peak bandwidth of 2.0 GByte/s in a single chip with low noise sensitivity, and (3) a flexible column redundancy scheme to efficiently increase redundancy coverage using a shifted I/O line scheme for multibank architecture.

Interface issues in displaying graphics and video on high resolution flat panel displays

As the PC market is poised to migrate rapidly from bulky CRTs to thin flat panel display (FPD) monitors, a number of interface issues must be resolved to enable and accelerate this transition. This paper addresses a few, but major FPD interface issues, including numerous signal wires, high clock speeds, and lack of a standard interface which prohibits interoperability for plug-and-play.