Design and analysis of a portable high-speed clock generator

Abstract

A new portable clock generator with full pull-in range and fast acquisition is presented in this paper, where it can be developed at hardware description language (HDL) to reduce design cycle as well as improve system-level integration simulation. In the proposed design, frequency tracking is performed by the Prune-and-Search algorithm, and the digital-controlled ring oscillator is constructed by CMOS standard cells. In order to reduce propagation delay of the loop divider, a novel structure is developed to provide a constant delay at any divider setting. In addition, input jitter can be isolated to avoid coupling by digital processing. Hence, the generated clock output becomes more clean and robust. Based on the proposed methodology, a test chip has been designed and verified on 0.6-/spl mu/m CMOS process with frequency range of (360 /spl sim/ 800) MHz at 3.3 V and peak-to-peak jitter of less than 60 ps at 800 MHz/3.3 V.