Timing constraints for high-speed counterflow-clocked pipelining

Abstract

With the escalation of clock frequencies and the increasing ratio of wire-to gate-delays, clock skew is a major problem to be overcome in tomorrow's high-speed very large scale integration (VLSI) chips. Also, with an increasing number of stages switching simultaneously comes the problem of higher peak power consumption. In our prior work, we have proposed a novel scheme called counterflow-clocked (C/sup 2/) pipelining to combat these problems, and discussed methods for composing C/sup 2/ pipelined stages. In this paper, we analyze in great detail the timing constraints to be obeyed in designing basic C/sup 2/ pipelined stages, as well as in composing C/sup 2/ pipelined stages. C/sup 2/ pipelining is well suited for systems that exhibit mostly unidirectional data flows as well as possess mostly nearest neighbor connections. C/sup 2/ pipelining eases the distribution of high-speed clocks, shortens the clock period by eliminating global clock signals, allows natural use of level-sensitive dynamic latches, and generates less internal switching noises due to the uniformly distributed latch operation. By applying C/sup 2/ pipelining and its composition methods to build a system, VLSI designers can substitute the global clock-skew problem with many local one-sided delay constraints.