High-speed Circuits Research Articles

Ultrafast Carbon Nanotube Photodetectors with Bandwidth over 60 GHz

The future interconnect links in intra- and inter-chip require the photodetector with high bandwidth, ultra-wide waveband, compact footprint, low-cost, and compatible integration process with silicon complementary metal-oxide-semiconductor (CMOS) technology. Here, we demonstrate a CMOS-compatible carbon nanotube (CNT) photodetector that exhibits high responsivity, high bandwidth and broad spectral operation over all optical telecommunication band based on high-purity CNT arrays. The ultrafast CNT photodetector demonstrates the 100 Gbit/s Nyquist-shaped on-off-keying (OOK) signal transmission, which can address the demand for high-speed optical interconnects in and between data centers. Furthermore, the photodetector exhibits a bandwidth over 60 GHz by scaling down the active area to 20 {\mu}m2. As the CNT photodetectors are fabricated by doping-free process, it also provides a cost-effective solution to integrate CNT photonic devices with CNT-based CMOS integrated circuits. Our work paves a way for future CNT-based high-speed optical interconnects and optoelectronic integrated circuits (OEICs).

A New Design of a 3 × 3 Reversible Circuit Based on a Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is the best-suggested nanotechnology for designing digital electronic circuits. It has a higher switching frequency, low-power expenditures, low area, high speed and higher scale integration. Recently, many types of research have been on the design of reversible logic gates. Nevertheless, a high demand exists for designing high-speed, high-performance and low-area QCA circuits. Reversible circuits have notably improved with developments in complementary metal–oxide–semiconductor (CMOS) and QCA technologies. In QCA systems, it is important to communicate with other circuits and reversible gates reliably. So, we have used efficient approaches for designing a [Formula: see text] reversible circuit based on XOR gates. Also, the suggested circuits can be widely used in reversible and high-performance systems. The suggested architecture for the [Formula: see text] reversible circuit in QCA is composed of 28 cells, occupying only 0.04[Formula: see text][Formula: see text]m2. Compared to the state-of-the-art, shorter time, smaller areas, more operational frequency and better performance are the essential benefits of the suggested reversible gate design. Full simulations have been conducted with the utilization of QCADesigner software. Additionally, the proposed [Formula: see text] gate has been schematized using two XOR gates.

Direct Measurement of Electrically Modulated Far-Field Thermal Infrared Emission and its Dynamics

Accurate direct measurements of far-field thermal infrared emission become increasingly important because conventional methods, relying on indirect assessments, such as reflectance/transmittance, are inaccurate or even unfeasible to characterize state-of-art devices with novel spectra, directionalities, and polarizations. The direct collection of the far-field emission from these tiny devices is also challenging because of their shrinking footprints and uncontrollable radiation noises from their surroundings. Here, we demonstrate a microscopic lock-in FTIR system that realizes significant improvement in signal-to-noise ratio (SNR) by combining a microscope and a lock-in amplifier with an FTIR. The lock-in FTIR is ultrasensitive, with a specific detectivity 10^6 times higher than commercial ones, to overcome the optical loss and background noise during the emission light collection. Based on an analytical model of the signal detection process, we also explore the combination of modulated Joule heating and global heating to fulfill the potential of our system for noise reduction. Our findings show that, compared to previous studies, more than 3 times lower temperatures are sufficient to generate a measurable signal. Under a heating temperature of around 125 {\deg}C, we can achieve an SNR of about 23.7, which is far above the true-signal-threshold (SNR of about 3.0). Furthermore, the system can respond fast enough (up to 175kHz) to record spectral-resolved dynamics of microdevices in the frequency domain. The measurable frequency range can be extended up to MHz or even GHz level by a high-speed circuit model. We believe the system together with the analytical signal processing can be beneficial for next-generation thermal infrared material and device exploration, boosting the applications in lighting, sensing, imaging, and energy harvesting on a small scale.

Overview of Common-Mode Noise Suppression Techniques: From Reflection to Absorption

Today’s fast-growing wireless communication technology has greatly increased the demand for the transmission of high-quality signals with high data rates. Because of its intrinsic advantages of high immunity to external noise, lower electromagnetic interference, harmonic suppression, and better linearity, differential signaling is preferable to single-ended signaling for many applications, including high-speed digital circuits, RF systems, and integrated circuits based on CMOS technology <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> , <xref ref-type="bibr" rid="ref3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[3]</xref> , <xref ref-type="bibr" rid="ref4" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[4]</xref> . However, in real-world circuit applications, differential signals are usually accompanied by destructive common-mode (CM) noise, which may be induced by asymmetric differential transmission paths with bending or length mismatch. On the other hand, imbalance of the differential signal channels, including amplitude swings and differences between rising and falling times, could also contribute to CM noise. In addition, the radiation emission caused by CM noise is much stronger than the differential signals, leading to a reduced system reliability <xref ref-type="bibr" rid="ref5" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[5]</xref> . Therefore, CM suppression has been an inevitable challenge for differential circuits and systems.

Label-free multiphoton imaging flow cytometry.

Label-free imaging flow cytometry is a powerful tool for biological and medical research as it overcomes technical challenges in conventional fluorescence-based imaging flow cytometry that predominantly relies on fluorescent labeling. To date, two distinct types of label-free imaging flow cytometry have been developed, namely optofluidic time-stretch quantitative phase imaging flow cytometry and stimulated Raman scattering (SRS) imaging flow cytometry. Unfortunately, these two methods are incapable of probing some important molecules such as starch and collagen. Here, we present another type of label-free imaging flow cytometry, namely multiphoton imaging flow cytometry, for visualizing starch and collagen in live cells with high throughput. Our multiphoton imaging flow cytometer is based on nonlinear optical imaging whose image contrast is provided by two optical nonlinear effects: four-wave mixing (FWM) and second-harmonic generation (SHG). It is composed of a microfluidic chip with an acoustic focuser, a lab-made laser scanning SHG-FWM microscope, and a high-speed image acquisition circuit to simultaneously acquire FWM and SHG images of flowing cells. As a result, it acquires FWM and SHG images (100 × 100 pixels) with a spatial resolution of 500 nm and a field of view of 50 μm × 50 μm at a high event rate of four to five events per second, corresponding to a high throughput of 560-700 kb/s, where the event is defined by the passage of a cell or a cell-like particle. To show the utility of our multiphoton imaging flow cytometer, we used it to characterize Chromochloris zofingiensis (NIES-2175), a unicellular green alga that has recently attracted attention from the industrial sector for its ability to efficiently produce valuable materials for bioplastics, food, and biofuel. Our statistical image analysis found that starch was distributed at the center of the cells at the early cell cycle stage and became delocalized at the later stage. Multiphoton imaging flow cytometry is expected to be an effective tool for statistical high-content studies of biological functions and optimizing the evolution of highly productive cell strains.

Design and Study of the Key Characteristics of a New DC Vacuum Interrupter With a High Peak and Low Residual Magnetic Field

With the rapid development of multiterminal high-voltage direct current (HVdc) transmission systems, the research and development of high-speed and stable high-voltage dc circuit breakers have received attention. Among them, mechanical dc circuit breakers based on manual zero-crossing dc breaking technology have been applied in practical projects, owing to their small size, low on-state loss, and low price. However, this method adds a high-frequency current, which deteriorates the magnetic field between the poles of the interrupter when the arc is broken. Therefore, the development of HVdc circuit breakers that maintain high peak magnetic fields and low residual magnetic fields at high frequencies has become the key to the development of multiterminal HVdc transmission. To solve this problem, this article proposes a new interrupter for a vacuum dc circuit breaker based on artificial zero-crossing technology and studies its key characteristics, such as temperature rise, electromagnetic field, and arc column plasma distribution characteristics. The results reveal that the new interrupter proposed in this article has a low-temperature rise, uniformly distributed electric field, high peak value and low remanence of the longitudinal magnetic field, and uniformly distributed plasma in the arc column, and exhibits arc diffusion. Its ability to cope with high-frequency current is significantly higher than that of the traditional cup-shaped axial magnetic field (AMF) contact system interrupter, which is conducive to the high-speed and stable breaking of the interrupter.

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

Aligned Carbon Nanotube Arrays with Germanium Protective Layers for Improving the Performance of Radio Frequency Transistors

Aligned carbon nanotube arrays with high semiconducting purity and high density have been regarded as an ideal channel material for constructing high-frequency field effect transistors and high-speed integrated circuits. However, contaminants (mainly resist residues) that leave the surface of carbon nanotubes during the fabrication process seriously deteriorate the interface contact quality, which will trigger large contact resistance and thus inhibit the ultimate performance of the carbon nanotube-based transistors. Here, we demonstrate a germanium protective layer technique that can keep a clean surface of carbon nanotube films from the contaminants during device fabrication and thus boost the quality of ohmic contact between carbon nanotubes (CNTs) and metal. The transfer length method (TLM) is used to evaluate the effect of the germanium protective layer technique on the ohmic contact resistance. The contact resistance from metal–CNTs extracted using the TLM was reduced by 93%, from 1.66 to 0.123 KΩ μm before and after the germanium process treatment. Owing to the great improvement of contact between metal and CNTs by introducing the germanium protective layer technique, the fabricated aligned CNT array-based radio-frequency field-effect transistors with a gate length of 110 nm on the quartz substrate present excellent DC performance, with an on-state current of 1.28 mA/μm and maximum transconductance of up to 1.05 mS/μm at a bias of −1.2 V. Meanwhile, the as-measured current gain cut-off frequency (fT,EXT) and power gain frequency (fMAX,EXT) increase from 12 to 110 GHz and 13 to 105 GHz, respectively. This approach provides a simple and reproducible means of improving the interface quality and reducing contact resistance in CNT-based devices to enhance performance.

A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process

This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the sampling phase to maximize the output-settling time of the operational amplifier (op-amp). A complete clocking scheme along with a delay lock loop (DLL) is proposed to generate an accurate timing no matter how process, voltage, and temperature (PVT) change. Based on PQT, a high-speed comparator circuit is adopted to obtain a bit error rate (BER) below 10−15. Sample and hold amplifier (SHA) is used to guarantee robustness over the wide input frequency. Furthermore, a low-cost automatic calibration is implemented to correct residual curves, and inter-stage gain errors are also corrected. This ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.3 dB and a spurious-free dynamic range (SFDR) of 78.5 dB at a 227 MHz input frequency. The measured differential nonlinearities (DNL) and integral nonlinearities (INL) after calibration are ±0.7 LSB and ±1.50 LSB, respectively. The power consumption of the ADC core is 97.6-mW, and the Walden figure of merit (FoM) is 172.9-fJ/conversion-step.

Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS

True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. Due to the relatively high leakage currents in modern CMOS processes, the use of leakage protection techniques of the storage nodes in TSPC must be considered, especially at high radiation doses. In this paper, the limitations originating from Total Ionization Dose (TID)-induced subthreshold leakage currents are analysed and radiation-hardening-by-design (RHBD) circuit techniques are proposed. Additionally, Single Event Upsets (SEU) are investigated by quantifying the critical charge of the leakage protected TSPC FF. The results are compared to both the static and the TSPC FF without leakage mitigation.

A High-Speed Low-Energy One-Trit Ternary Multiplier Circuit Design in CNTFET Technology

Contemporary system-on-chip-based applications are battery-powered. To increase the operation time, they need various low-power/energy circuits. Carbon nanotube field-effect transistor (CNTFET) is a potential alternative to complementary metal-oxide-semiconductor for power/energy-efficient circuits implementation due to offering high performance. Another way to reduce power/energy consumption in a circuit is to use multiple-valued logic, especially ternary logic, which has three logical states. This paper presents a novel 1-trit ternary multiplier circuit with 23 transistors based on only unary operators of the ternary logic system and the dual-supply voltages technique. The proposed design does not use the ternary decoder/encoder, logic gates, cascading transmission gates, and ternary multiplexer to reduce the transistors count, delay, power, and energy. The Stanford CNTFET model in the 32 nm technology node is used to simulate the proposed design. The delay, power, and delay-power-product (PDP) of the proposed design at 0.9 V are 0.026 ns, 0.139 μW, and 3.614 aJ, respectively. It offers improvements between 50% and 61.19% in delay and between 52.72% and 59.75% in PDP compared to previously published multiplier circuits, which are based on the dual-supply voltages and use 23 transistors. These improvements make the proposed design a good candidate for the design of the next generation of multiplier circuits in arithmetic blocks.

Design and Research of Channel Circuit Based on Broadband Power Line Carrier

In order to effectively improve the anti-attenuation, anti-noise and anti-impedance change capabilities of the low-voltage narrowband power line carrier communication unit, reduce the carrier signal coupling attenuation, and highly fidelity signal power encoded and modulated by the carrier chip, an improved high-speed power line carrier communication transceiver circuit is designed. Using 303.13kHz~357.81kHz as sub-carrier signal frequency can effectively avoid the random noise generated by high-power power electronic equipment and household appliances below 35kHz. At the same time, to prevent the frequency crosstalk of power line carrier products with 270kHz and 421kHz as the center frequency, the Y-coupling capacitor and sixth order Butterworth band-pass filter circuit are used to design the signal receiving and transmitting circuit of the communication unit to isolate unwanted signals. The experimental simulation of the designed circuit is carried out on the circuit simulation software Multisim 12. The results show that the designed power line carrier communication transceiver circuit can effectively control the signal coupling attenuation within 4dB, and the filtering of unwanted signals can also reach 41.7dB, which has good application value.

Temperature-Insensitive Ka-Band Transceiver With Ultralow-Noise Self-Calibrated Low Dropout Regulator in 65-nm CMOS

This article proposes a Ka-band transceiver with an integrated local oscillator (LO) generator and multiple low dropout regulators (LDOs) to eliminate the strict requirements to the external power supply network. The proposed self-calibrated LDO eliminates the use of a bandgap reference circuit and its large flicker noise contribution in traditional power regulators to achieve ultralow-noise performance. The output of the proposed LDO is self-calibrated with temperature and process variations by autoconfiguring the feedback coefficient through a digital loop to guarantee the stable performance of its loaded high-speed circuits. The stable gain and output power of the transceiver with temperature variation are achieved by on-chip multiple self-compensation schemes, which include a self-sensing LDO for the power amplifier, a constant- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{\!m}$ </tex-math></inline-formula> bias circuit for the amplification stages, and the temperature-compensated intermediate-frequency amplifiers (TC IFAs) with proportional-to-absolute-temperature (PTAT) gain to further compensate for the gain deviation caused by the second-order effect and large-signal performance difference. Implemented in 65-nm CMOS technology, measurements indicate that the output noise of the proposed LDO is as low as 15 nV/sqrt (Hz) at 10-kHz offset and the integrated power network greatly reduces the noise influence on the LO signal compared with the traditional bandgap-referenced LDO. Furthermore, due to the adoption of the proposed temperature compensation scheme, the small-signal gains of the receiver and transmitter only fluctuate by 1.1 and 1.3 dB from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40\,\,^{\circ }\text{C}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$85~^{\circ }\text{C}$ </tex-math></inline-formula> , respectively, and the output saturated power of the transmitter varies by 0.7 dBm over the entire temperature range.

Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits

The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.

Tree-Based Machine Learning Models with Optuna in Predicting Impedance Values for Circuit Analysis.

The transmission characteristics of the printed circuit board (PCB) ensure signal integrity and support the entire circuit system, with impedance matching being critical in the design of high-speed PCB circuits. Because the factors affecting impedance are closely related to the PCB production process, circuit designers and manufacturers must work together to adjust the target impedance to maintain signal integrity. Five machine learning models, including decision tree (DT), random forest (RF), extreme gradient boosting (XGBoost), categorical boosting (CatBoost), and light gradient boosting machine (LightGBM), were used to forecast target impedance values. Furthermore, the Optuna algorithm is used to determine forecasting model hyperparameters. This study applied tree-based machine learning techniques with Optuna to predict impedance. The results revealed that five tree-based machine learning models with Optuna can generate satisfying forecasting accuracy in terms of three measurements, including mean absolute percentage error (MAPE), root mean square error (RMSE), and coefficient of determination (R2). Meanwhile, the LightGBM model with Optuna outperformed the other models. In addition, by using Optuna to tune the parameters of machine learning models, the accuracy of impedance matching can be increased. Thus, the results of this study suggest that the tree-based machine learning techniques with Optuna are a viable and promising alternative for predicting impedance values for circuit analysis.

Homogeneous, lossy and Asymmetrical Strip Line with tabbed design for High-Speed Interface application

Reduction of cross talk noise is an important characteristics of clean signal quality for high-speed channel analysis. In this paper, tab added strip line is modelled to improve signal distortion in high-speed digital circuits. A comprehensive analysis of the proposed design is done across frequency domain and time domain. 6dB improvement of FEXT is observed during frequency domain analysis and 3mV in eye height of time domain analysis.

Correlation between the magnitude of interlayer exchange coupling and charge-to-spin conversion efficiency in a synthetic antiferromagnetic system

The correlation between the magnitude of interlayer exchange coupling (J ex) and charge-to-spin conversion efficiency (spin Hall angle: θ SH) is investigated in a synthetic antiferromagnetic (AF) system with compensated magnetization. The magnitude of θ SH increases linearly with increasing the magnitude of J ex. We observe the factor of 6.5 increase of spin Hall angle (θ SH = 45.8%) in a low resistive (ρ xx = 41 μΩcm) synthetic AF system by increasing the magnitude of J ex. The low resistive synthetic AF system will be a promising building block for future nonvolatile high-speed memories and logic circuits using the spin Hall effect.

External Partial Discharge Detection of Gas-Insulated Switchgears Using a Low-Noise and Enhanced-Sensitivity UHF Sensor Module

Ultra-high frequency (UHF) partial discharge (PD) detection is essential for routine maintenance of gas-insulated switchgear (GIS). Realizing low-noise detection with cost-effectiveness and ease of installation is promising but challenging. This paper presents a novel broadband noise-shaping network (BNSN) integrated with a printed monopole antenna (PMA) sensor to realize sufficient noise rejection and good impedance matching. Moreover, by analyzing the equivalent noise circuit and codesigning a high-speed preamplifier circuit with the proposed sensor, the detection sensitivity and anti-interference of the proposed sensor module are improved. The effectiveness and superiority of the proposed sensor are first verified in accordance with IEC 62478, followed by validations using a PD simulator and a real 24-kV GIS. The experimental results demonstrate that the proposed sensor module has the capability to identify different PD types even in noisy environments.

Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor (CMOS)-based Very Large-Scale Integration (VLSI) circuit designs. Positive Channel Metal Oxide Semiconductor (PMOS) has been replaced by Negative Channel Metal Oxide Semiconductor (NMOS) in recent years, with low dimension-switching changes in order to shape the mirror of voltage comparator. NMOS is used to reduce stacking leakage as well as total exchange. Domino Logic Circuit is a powerful and versatile digital programmer that gained popularity in recent years. In this study regarding Adaptive Sub Threshold Voltage Level Control Problem, the researchers intend to solve the contention issues, reduce power dissipation, and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control (ASVLC)-based domino circuit. The efficiency and effectiveness of the domino circuit are demonstrated through simulation results. The suggested system makes use of high-speed broad fan-gate circuits, occupies minimum space, and consumes meagre amount of power. The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V, frequency of 100 MHz, and an operating temperature of 27°C with 64 input OR gates. As per the simulation results, the suggested Domino Gate reduced the power dissipation by 17.58 percent and improved the noise immunity by 1.21 times in comparison with standard domino logic circuits.

Analytical Modeling of Deterministic Jitter in CMOS Inverters

With the advancement of semiconductor technology (enabling the dimensions of the switching devices in the range of nanometer scale) designing, modeling, and optimization of high-speed circuits are becoming very complicated. Various issues related to signal and power integrity come into picture at high-frequency operations, e.g. jitter, cross-talk, electromagnetic interference etc. In this article, an analysis of the CMOS inverter in presence of deterministic noise is presented. An analytical approach is presented which estimates jitter in CMOS inverters in the presence of Power Supply Noise (PSN), Data Noise (DN), and Ground-Bounce Noise (GBN) by deriving analytical relationships. The proposed analytical method takes into account the device parameters to model timing uncertainty. The expression for jitter is obtained by estimating the deviation of each transition edge from its ideal position. Several examples (simulations as well as measurement) are presented to validate the proposed modeling. These examples include comparing the analytical results with the simulation results obtained using an SPICE based simulator as well as doing the same with the experimental results using two different CMOS inverter Integrated Circuits (ICs). In order to test the independence of the proposed modeling approach on a specific technology node, the results are verified by considering different technology nodes such as: 40 nm, 65 nm, and 180 nm from United Microelectronics Corporation (UMC). Also, two different ICs (M74HC04, and MC74AC04 N) from different vendors are used for measurement. The results obtained using the proposed methodology are in close consonance with those obtained from simulations using the EDA tool and the experiments.