High-speed Circuit Applications Research Articles

Leakage reduction technique for nano-scaled devices

PurposeThe purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.Design/methodology/approachBecause of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.FindingsThis study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.Originality/valueAll the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

Du Pont and IQLP to further develop and refine liquid crystal polymer (LCP) thin-film technology for use in high-speed circuit applications

Du Pont and IQLP to further develop and refine liquid crystal polymer (LCP) thin-film technology for use in high-speed circuit applications

High-speed driver with built-in self detection functions for off-chip transmission

Although low-voltage differential signaling (LVDS) is one of the very popular technologies which simultaneously address low dynamic power consumption and high data rate transmission in modern high speed circuit applications. However, signal integrity at receiving ends will be strongly dependent on the off chip transmission path even using LVDS transmission technique. In this paper, we propose a novel high-speed off chip data transmission driver with built-in self detection functions which include frequency detection and duty-cycle detection capabilities. With these built-in detection functionalities, we can monitor signal quality at the end of off-chip transmission path no matter which kind of transmission path system user chooses. Besides, users can also utilize the detection information to make adjustment on the input signal at the beginning of transmission path. Therefore, the novel proposed transmission driver simultaneously posses high-speed and good signal integrity for off-chip transmission applications. The design was implemented using standard 3.3 V 0.35 μm CMOS technology with overall chip size of 0.91 mm2. Simulation and measurement results both successfully verify the novelty and achievement of this work.

Design and realization of 1.3 Gb/s off-chip transmission circuitry using 0.35 μm CMOS technology

Low-voltage-differential-signaling (LVDS) is one of the very popular technologies which simultaneously addresses low dynamic power consumption and high data rate transmission in modern high speed circuit applications. In this paper, system level integration design approach is applied to design LVDS transmitter featuring high off-chip data rate. Full wave electromagnetic simulation technique was adopted to accurately characterize possible couplings and parasitic effects induced from the off-chip components which then acted as the termination of the output circuitry. Common mode feedback was included to perform fine tuning on the offset leading to much higher overall precision. Meanwhile, generation of the controlled current and voltage across termination was guaranteed through the introduction of a constant transconductance bias network. The design was implemented using TSMC 3.3 V 0.35 μm CMOS technology with overall chip size of 0.923 mm2. At a DC power consumption level of 29.4 mW, the LVDS transmitter exhibited an off-chip data rate of 1.3 Gb/s validated through measurements.

A Comprehensive Delay Model for CMOS CML Circuits

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <?Pub Dtl=""?>MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional <emphasis emphasistype="italic">RC</emphasis> delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional <emphasis emphasistype="italic">RC</emphasis> delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general <emphasis emphasistype="italic">RC</emphasis> delay model format. Theoretical results are compared with Spice simulations in a 0.13-<formula formulatype="inline"><tex>$\mu{\hbox {m}}$</tex></formula> CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple <emphasis emphasistype="italic">RC</emphasis> delay model fails to provide. </para>

Pulsewidth control loop with tunable duty cycle for high-speed circuit applications

To meet the demand of the state-of-the-art high-speed double data rate systems, the precise system timing plays an important role since both rising and falling edges of the system clock signal are employed to sample the input data. Owing to this requirement, it is necessary to accurately maintain the duty cycle of the clock signal at 50%. A pulsewidth control loop (PWCL) circuit was therefore proposed to adjust the duty cycle of the output signal of a multistage clock buffer. The main theme of the paper is aimed at introducing a newly proposed differential PWCL (DPWCL) together with investigating its mechanism through a comprehensive theoretical analysis that also demonstrates the settling speed of the proposed DPWCL is much faster than the conventional PWCL. Alternatively, the proposed DPWCL employs a low-pass filter to generate the reference voltage for the balanced charge pump so that the DPWCL does not necessitate a 50% duty cycle reference clock. A duty cycle tuning mechanism based on the proposed DPWCL is also presented.

Ultra high-speed InP-InGaAs SHBTs with f/sub max/ of 478 GHz

InP-based single heterojunction bipolar transistors (SHBTs) for high-speed circuit applications were developed. Typical common emitter DC current gain (/spl beta/) and BV/sub CEO/ were about 17 and 10 V, respectively. Maximum extrapolated f/sub max/ of 478 GHz with f/sub T/ of 154 GHz was achieved for 0.5 /spl times/ 10 /spl mu/m/sup 2/ emitter size devices at 300 kA/cm/sup 2/ collector current density and 1.5 V collector bias. This is the highest f/sub max/ ever reported for any nontransferred substrate HBTs, as far as the authors know. This paper highlights the optimized conventional process, and the authors have great hopes for the process that offers inherent advantages for the direct implementation to high-speed electronic circuit fabrication.

Dry-etch fabrication of reduced area InGaAs/InP DHBT devices for high speed circuit applications

We have fabricated reduced area InGaAs/InP DHBTs for high speed circuit applications. To produce the small dimensions required, a process involving both wet chemical and ECR plasma etching was developed. Optical emission spectroscopy was used for end-point detection during plasma etching. With this improved process, an ft of 170 and fmax of 200 GHz were achieved for 1.2 × 3 µm2 emitter size devices with a 500 A base.

Capacitance-voltage characteristics and cutoff frequency of pseudomorphic (AlGaAs/InGaAs) modulation-doped field-effect transistor for microwave and high-speed circuit applications

A two-dimensional analytical model for the capacitance–voltage characteristics of a pseudomorphic AlGaAs/InGaAs modulation-doped field-effect transistor is developed using charge-control analysis for its microwave frequency applications. The model includes the effect of various fringing field capacitances, and a cutoff frequency of 94.8 GHz is obtained for an L=0.25 μm device. The effect of traps has been included, which decreases the cutoff frequency. The results so obtained are compared with experimental data, and show excellent agreement, thereby proving the validity of the model. ©1999 John Wiley & Sons, Inc. Microwave Opt Technol Lett 23: 312–318, 1999.

Novel fabrication of C-doped base InGaAs/InP DHBT structures for high speed circuit applications

We have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter–base and base–collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter–base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8-10 V, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in d.c. characteristics after operation at an emitter current density of 90 kA cm −2 and a collector bias, V CE, of 2 V at room temperature for over 500 h. Typical common emitter current gain was 50. An f t of 80 and f max of 155 GHz were achieved for 2×4 μm 2 emitter size devices.

High-performance heterostructure field-effect transistors (HFETs) with step-modulationed InGaAs channel structure

Two types of new heterostructure field-effect transistors are fabricated and investigated in this paper. The pseudomorphic In x Ga 1 − x As ( x < 0.2) and Al 0.3Ga 0.7As (or In 0.49Ga 0.51P) layers are used as the active channel and Schottky contact layer, respectively, in these studied devices. Owing to the large conduction band discontinuity (Δ E C) at In x Ga 1 − x As/Al 0.3Ga 0.7As and In x Ga 1 − x As/In 0.49Ga 0.51P interfaces, the carriers can be easily confined in the channels. Thus the device characteristics such as drain saturation current, breakdown voltage and transconductance ( g m) are improved. Furthermore, by varying the doping concentration or In composition in the channel, both the high carrier density and high output current may be obtained as a result of the significant carrier accumulation effect. From the experimental results, these studied devices show their great potential in high-power and high-speed circuit applications.

Integration of InAlAs/InGaAs/InP enhancement- and depletion-mode high electron mobility transistors for high-speed circuit applications

A process for the monolithic integration of enhancement- and depletion-mode high electron mobility transistors (E/D-HEMTs) on InAlAs/InGaAs/InP is reported. The E-HEMTs with a 1.0-/spl mu/m gate length exhibit a threshold voltage of +255 mV and a maximum dc extrinsic transconductance of 503 mS/mm at room temperature, while a threshold voltage of -317 mV and a transconductance of 390 mS/mm are measured for the D-HEMTs of the same gate length. The devices show excellent RF performance, with a unity current-gain cutoff frequency (f/sub t/) of 35 GHz and a maximum frequency of oscillation (f/sub max/) of 95 GHz for both the E- and D-HEMT's. To the best of the authors' knowledge, this is the first demonstration of an E/D-HEMT technology on lattice-matched InP that is suitable for circuit integration.

Novel Fabrication of C-Doped Base InGaAs/InP DHBT Structures For High Speed Circuit Applications

AbstractWe have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter-base and base-collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter-base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8V to IOV, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in DC characteristics after operation at an emitter current density of 90kA/cm2 and a collector bias, VCE, of 2V at room temperature for over 500 hours. Typical common emitter current gain was 50. An ft of 80 and fmax of 155 GHz were achieved for 2 × 4 μm2 emitter size devices.

Low-current operation of high-speed InP/InGaAs heterojunction bipolar transistors

High-speed performance, f T > 100 GHz, at sub-milliampere collector currents is demonstrated with a laterally scaled-down InP/InGaAs heterojunction bipolar transistor (HBT) fabricated by using a combination of dry and wet etching techniques. This result indicates that small-sized InP/InGaAs HBTs are promising for low-power high-speed circuit applications. To cope with the characteristic problems of the small-sized devices, i.e. degraded current gain and increased base resistance, the influence of graded-base structure and emitter geometry on transistor performance is investigated with the result that the graded-base structure is effective for enhancing current gain, and that narrowing the emitter stripe width is effective for suppressing the increase in base resistance.

Two-temperature technique for plasma-enhanced chemical vapour deposition growth of silicon-nitride on InP

The high mobility and saturated drift velocity of electrons in InP make the insulator/InP structure very attractive for high speed circuit applications. Despite this potential, however, a number of troubling problems, such as high density of interface states, formation of poor dielectrics, electrical instability and lack of reproducibility, remain to be solved. The established deposition methods can not satisfy simultaneously the requirements for low density of interface states and good dielectric properties of insulator [1]. The newly proposed twotemperature deposition technique offers a possible way of solving this problem [2]. In this method, a thin interracial layer is formed at a low temperature, then the bulk insulator is deposited at a higher temperature. The value of this technique has been proven for the SiO2/Si system. To the best of our knowledge, however, the application of this technique to insulator/III-V semiconductor has not been reported. In this letter, we report on the results of the two-temperature technique applied to form an SIN,/ InP structure, where SiN, was produced by the plasma-enhanced chemical vapour deposition (PECVD) method. The electrical properties were characterized by multifrequency capacitancevoltage ( C V ) measurements, 1 MHz conductance-voltage ( G V ) measurements and quasi-static C V measurements. The optimum deposition temperature was found to be about 200 °C for the first thin SiN, deposition. The substrates employed in this study were undoped n-type (n--~ 5.0 x 1015 cm -3) (100) InP wafers (Nippon Mining Co.). The wafers were first cleaned in a standard organic solution (trichloroethylene, acetone and methanol). To remove any native oxide on the surface, they were then etched with acid solution (H2SO4:H202:H20 = 3:1:1) for 60 s. After rinsing in deionized water, they were dried by N2 gas blow. After blowing, the SiN, deposition process was initiated immediately in the PECVD chamber. The PECVD apparatus used was designed inhouse and the reactor was a capacitivelycoupled hot wall type [3]. Silicon nitride films were deposited from the gas mixture of dilute silane (5% Sill 4 in N2), ammonia (99.999%) and nitrogen

The preparation of epitaxial InSb films by magnetron sputtering

InSb, with its narrow bandgap, has found application in a wide variety of infrared detector applications, ranging from infrared astronomy on the Galileo satellite to tactical weapon guidance systems. However, InSb also demonstrates an extremely high electron mobility, up to 1 000 000 cm2∙V−1∙s−1 at 77 K, which makes it of particular interest for very high-speed circuit applications. In the past, most multilayer InSb structures have been prepared by conventional crystal-growth techniques, including liquid-phase epitaxy, metalorganic chemical vapour deposition, and molecular-beam epitaxy. In this presentation, the preparation of thin epitaxial films of InSb by magnetron sputtering will be discussed. Using this technique, we have deposited good quality epitaxial InSb films on [Formula: see text] InSb and [Formula: see text] GaAs. In this study, the effects of substrate temperature and sputter pressure on film morphology, composition, and growth rate are examined. As well, preliminary measurement of the electrical characteristics of these layers and their crystal quality as determined by X-ray diffraction and large-area electron-channelling pattern analysis are presented.

Radiation-Hardened Silicon-Gate CMOS/SOS

High performance, radiation hardened silicon gate CMOS/SOS circuits have been fabricated. Radiation hardness was achieved by using a low temperature (875°C), wetprocess gate oxide, and by minimizing the temperature of subsequent process steps. The need for additional temperature steps was eliminated by in-situ doping of the polysilicon gate material with boron and by using ion-implantation instead of diffusions to form source and drain regions. Radiation effects in simple inverter circuits have been measured. Threshold shifts after 106 rads (Si) of ionizing radiation are #x02264;0.5 V for n-channel transistors and #x02264;1. 6 V for p-channel transistors. Irradiation of p-channel transistors in circuit configurations where effective positive gate voltages occur, results in a 4 V shift at 106 rads (Si). Ring oscillator circuits have been fabricated to measure intrinsic circuit performance. With a 15 V power supply, stage delays of 0.5 ns are achieved. These short stage delays verify the suitability of the fabrication process for high speed circuit applications.