A Comprehensive Delay Model for CMOS CML Circuits

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <?Pub Dtl=""?>MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional <emphasis emphasistype="italic">RC</emphasis> delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional <emphasis emphasistype="italic">RC</emphasis> delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general <emphasis emphasistype="italic">RC</emphasis> delay model format. Theoretical results are compared with Spice simulations in a 0.13-<formula formulatype="inline"><tex>$\mu{\hbox {m}}$</tex></formula> CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple <emphasis emphasistype="italic">RC</emphasis> delay model fails to provide. </para>