High-speed Arithmetic Research Articles

Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

A Review of Vedic Mathematics for the Design of High-Speed Arithmetic RISC Processors

Vedic Mathematics is a collection of techniques and concepts developed from ancient Indian mathematical books known as the Vedas. These strategies are designed to make different mathematical computations easier and faster. High-throughput RISC Processor Design, on the other hand, includes the creation of processors that prioritize the execution of a high number of instructions per unit of time. If there have been breakthroughs relating to Vedic Mathematics and High-Throughput RISC Processor Design, it would be intriguing to investigate how these old mathematical ideas may be utilized to improve the efficiency of current processor designs. Give a summary of the work, stressing the potential benefits and drawbacks of incorporating Vedic Mathematics concepts into the design of High-Throughput RISC computers. Introduce Vedic Mathematics and High-Throughput RISC Processor Design separately. Explain briefly why you're looking at incorporating Vedic Mathematics into CPU architecture. Outline key Vedic Mathematics concepts that may be applied to processor design. What distinguishes these ideas from typical mathematical approaches Provide an overview of the fundamental ideas and issues involved in the design of high-throughput RISC processors. Emphasize the critical areas for improvement and integrating principles from Vedic Mathematics into Processor Architecture: Investigate the use of Vedic Mathematics principles in processor architecture to discuss how these concepts may be utilized to solve specific problems or improve aspects of high-throughput RISC architectures. The importance of multipliers in Arithmetic Unit performance is underlined. The incorporation of Vedic Science, an ancient mathematical system comprised of 16 Sutras, implies a fresh method for arithmetic computations. The suggestion comprises optimizing the Vedic multiplier type Urdhva Triyakbhyam by substituting Convey Save Viper for the usual carry. This is done to reduce delays caused by standard adders and incomplete products aspire to outperform traditional designs in terms of speed. The explicit data on the speed gains is obtained and how they were assessed will bolster the claims and utilization of the proposed proficient Vedic multiplier in the number juggling module of the RISC processor. In addition, stating its application in the field of digital signal processing (DSP) broadens the scope of work. Validation of RTLs and FPGAs for the Register-Transfer Level (RTL) implementation of the proposed Math Unit in VHDL, paired with simulation using Xilinx ISE EDA tools, is a useful step in verifying the design. Validation on an FPGA device, especially a Vertex-IV, provides credibility to the suggested solution.

A New Keeper Domino Logic Based Full Adder for High-Speed Arithmetic Circuits

Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve the power delay product of the dynamic logic using carbon nanotube MOSFET. Methods: As a benchmark, a one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40%, respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using Si-MOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50%, respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications

This paper presents the implementation and design of Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared them for best optimized multiplier. The number of parital products generation can be reduced by n/3 by using radix-8 in the multiplier encoding. To further reduce the additions we have used booth recoding mechanism .We have implemented the design using Kogge stone adder and Brent kung adder. We observed that by using parallel prefix adders reduces the delay further more which results in significant increase in speed of the digital systems. The simulation results are carried out on XILINX VIVADO software.

Using Floating-Point Intervals for Non-Modular Computations in Residue Number System

The residue number system (RNS) provides parallel, carry-free, and high-speed arithmetic and is therefore a good tool for high-performance computing. However, operations such as magnitude comparison, sign computation, overflow detection, scaling, and division are difficult to perform in RNS, since it is problematic to determine the magnitude of an RNS number. In order to resolve this problem, we propose to compute the interval evaluation of the fractional representation of an RNS number in floating-point arithmetic of limited precision. No matter what the size n of the moduli set and dynamic range, only small arithmetic operations are required, and most of the computations are performed in parallel with n threads, which allows for efficient implementation of our method on many general-purpose computing platforms. Using this method, we propose new algorithms for magnitude comparison and general division in RNS and implement them for GPUs using the CUDA platform. We evaluate the performance of our algorithms on an NVIDIA GTX 1080 GPU using sets of 4 to 256 RNS moduli that provide dynamic ranges from 64 to 4096 bits. Experimental results show that the proposed new algorithms are efficient for large moduli sets and clearly outperform the existing RNS magnitude comparison and division algorithms in terms of execution time.

Performance Efficient Alu using Finfet

According to the prophecy of Moore, the concentration of transistors in an integrated circuit doubles every two years. But this is limited by the technologies used in the fabrication of integrated circuits, as the systems are scaled down. FinFET technology aims to combat this challenge. The construction of power efficient high speed Arithmetic & Logical Unit (ALU) using FinFET technology is proposed in this paper. Proposed FinFET based ALU is designed with arithmetic functions like high speed addition, multiplication and logical functions such as AND and XOR. Simulation results of the proposed power efficient high speed FinFET ALU proves to be better with a power saving of 80.5%. FinFET has the advantage of providing low power without compromising on the Performance. The power analysis for ALU is done using CADENCE-VIRTUOSO, which is known for its accuracy.

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

A Ternary Full Adder Cell Based on Carbon Nanotube FET for High-Speed Arithmetic Units

A Ternary Full Adder Cell Based on Carbon Nanotube FET for High-Speed Arithmetic Units

High Speed Arithmetic Logic Unit

High Speed Arithmetic Logic Unit

Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm

A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power consumption.

IJIREEICE - Electrical, Electronics, Instrumentation and Control

2 Abstract: The aim of this paper is to give a review of VLSI architectures for 2-DWT implementation of wavelet transform by using 4 Booth multiplier. This review paper describes implementation of radix-4 Modified Booth Multiplier and this implementation is compared with Radix-2 Booth Multiplier. Modified Booths algorithm employs both addition and subtraction and also treats positive and negative operands uniformly. Parallel MAC is frequently used in digital signal processing and video/graphics applications. A new architecture of multiplier and accumulator (MAC) for high speed arithmetic by combining multiplication with accumulation and devising a carry-look ahead adder (CLA), the performance is improved. Modified Booth multiplication algorithm is designed using high speed adder. High speed adder is used to speed up the operation of Multiplication. Designing of this algorithm is done by using VHDL and simulated using Modelsim SE 16.3f software has been used and implemented on Matlab R2013b. This paper proposes the design and implementation of Booth multiplier using VHDL. This compares the power consumption and delay of radix 2 and modified radix 4 Booth multipliers. We can achieve the Experimental results demonstrate that the modified radix 4 Booth multiplier has 22.9% power reduction than the conventional radix 2 Booth Multiplier and near about 50% power reduction than the conventional Normal Booth Multiplier

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

A Carry-Select Adder (CSA) is one of the most suitable adders for high-speed applications, but the power and area penalties are greater, because it requires a double Ripple-Carry Adder (RCA) structure corresponding to carry inputs 0 and 1. Current low-power and low-area techniques are not suitable for a standard cell-based design which is one of the widely adopted design methodologies. Our work proposes two simple optimised architectures suitable for standard cell-based designs. A simple decision logic that replaces the RCA for Carry input 1 in a conventional CSA is proposed. One of the proposed architectures reduces power and area significantly with a small delay penalty compared to the existing techniques. Another proposed architecture improves the speed of operation and reduces the power and area considerably. The first one is more suitable for high-speed arithmetic in battery-operated applications where there is a trade-off between speed and power, while the other one is suitable for high-performance applications which also require area and power optimisation. The proposed architectures were implemented in TSMC 0.18um CMOS technology, and compared with conventional Square Root Carry-Select Adders and an existing standard cell-based design.

Ancient Vedic Multiplication Based Optimized High Speed Arithmetic Logic

Here, we deal with most effective Vedic multiplication method dependent 4*4 bit arithmetic logic unit having high speed. In this paper, we will perform ALU operations. ALU is a development of research work that has been done for years so we have chosen this topic. Normally ALU is a heart of digital processor, central processing unit, microprocessor and micro controller. Every digital domain based technology has to depend on the performance of ALU. Hence, there is a necessity of ALU which generates high speeds which depends on the speed of multiplier. Therefore, we go for designing a 4-bit multiplier. To generate high speeds, multiplier is employed which is one of the important blocks of the hardware unit and also an important initiation of delay in the path. We have studied many algorithms for multiplication technique but research says that Vedic multiplication is most effective of all in terms of speed. The algorithm contains 16 sutra, out of which we are employing URDHVA TIRYAKBHYAM and the code is written in Very High Speed Integrated Circuit Hardware Description. Our supporting synthesizing and simulating tools are Xilinx ISE9.2i and model sim-altra6.3g-pi (Quartus II) respectively. At last, we will compare 4-bit ALU with 4-bit Array ALU.

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

Novel Architecture of High Speed Parallel MAC using Carry Select Adder

In this paper, new hardware architecture of multiplier and accumulator (MAC) for high speed arithmetic was designed. The performance was improved by merging multiplication with accumulation and organize a hybrid type carry save adder (CSA).The proposed CSA tree uses 1‟s complement based radix-4 and radix-8 modified booth algorithm(MBA). The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to reduce the number of the input bits of the final adder. This MAC add the intermediate results in the form of sum and carry bits instead of the final adder output, which made it possible to optimize the pipeline system to improve the performance. The final addition was carried out by high speed carry select adder (CSLA) with binary to excess convertor using CLA. Based on the theoretical and experimental estimation, we analyzed the results in terms of delay. The design is implemented using VHDL language and simulated using Xilinx ISE10.1 Simulator.

VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix -2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Design and Performance Analysis of Hybrid Adders for High Speed Arithmetic Circuit

Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.

A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations

A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

A new transistor sizing algorithm, SEA (Simple Exact Algorithm), for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP), chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.