High Slew Rate Research Articles

Merged Flyback–SC-Based Output Stage for Versatile Portable Transcutaneous Electrical Stimulators

This paper introduces a highly flexible multichannel output stage for battery-powered portable electric stimulators (ESs), based on novel power converter architecture. Compared with other solutions, the presented output stage for transcutaneous (surface) stimulations increases the number of applicable therapies, improves the battery operating time through reduced power consumption, and potentially results in more comfortable and shorter healing therapies. The new hybrid switch-mode power converter is a combination of flyback and switched-capacitor (SC) topologies. The flyback steps up the battery voltage and provides galvanic isolation. The following power-efficient SC stage replaces lossy linear current sources (CSs) of conventional solutions and produces pulses with a much higher slew rate, reducing the pulse energy needed to cause the stimulus. The SC also inherently produces pulses with zero-net charge, eliminating bulky blocking capacitors and/or dedicated discharging circuits. The regulation of the amplitudes of the pulses is performed with a new digital voltage-programmed current mode controller, forcing the output of the SC stage to behave as a CS. The flexible digital controller allows for creation of various types of pulses and also features several levels of patient protection. An experimental prototype of the output stage has undergone proof of principle tests with able-bodied individuals. The results show that the new output stage produces pulses with a 1-mA/ns slew rate, about two orders of magnitude higher than the other known solutions. The trials show that the faster slew rate pulses generate the same muscle contraction with 34% lower amplitudes, reducing energy consumption by 55%, allowing longer battery life of portable ES applications.

High slew-rate head-only gradient for improving distortion in echo planar imaging: Preliminary experience.

To investigate the effects on echo planar imaging (EPI) distortion of using high gradient slew rates (SR) of up to 700 T/m/s for in vivo human brain imaging, with a dedicated, head-only gradient coil. Simulation studies were first performed to determine the expected echo spacing and distortion reduction in EPI. A head gradient of 42-cm inner diameter and with asymmetric transverse coils was then installed in a whole-body, conventional 3T magnetic resonance imaging (MRI) system. Human subject imaging was performed on five subjects to determine the effects of EPI on echo spacing and signal dropout at various gradient slew rates. The feasibility of whole-brain imaging at 1.5 mm-isotropic spatial resolution was demonstrated with gradient-echo and spin-echo diffusion-weighted EPI. As compared to a whole-body gradient coil, the EPI echo spacing in the head-only gradient coil was reduced by 48%. Simulation and in vivo results, respectively, showed up to 25-26% and 19% improvement in signal dropout. Whole-brain imaging with EPI at 1.5 mm spatial resolution provided good whole-brain coverage, spatial linearity, and low spatial distortion effects. Our results of human brain imaging with EPI using the compact head gradient coil at slew rates higher than in conventional whole-body MR systems demonstrate substantially improved image distortion, and point to a potential for benefits to non-EPI pulse sequences. J. Magn. Reson. Imaging 2016;44:653-664.

Technical Note: Compact three-tesla magnetic resonance imager with high-performance gradients passes ACR image quality and acoustic noise tests.

A compact, three-tesla magnetic resonance imaging (MRI) system has been developed. It features a 37 cm patient aperture, allowing the use of commercial receiver coils. Its design allows simultaneously for gradient amplitudes of 85 millitesla per meter (mT/m) sustained and 700 tesla per meter per second (T/m/s) slew rates. The size of the gradient system allows for these simultaneous performance targets to be achieved with little or no peripheral nerve stimulation, but also raises a concern about the geometric distortion as much of the imaging will be done near the system's maximum 26 cm field-of-view. Additionally, the fast switching capability raises acoustic noise concerns. This work evaluates the system for both the American College of Radiology's (ACR) MRI image quality protocol and the Food and Drug Administration's (FDA) nonsignificant risk (NSR) acoustic noise limits for MR. Passing these two tests is critical for clinical acceptance. In this work, the gradient system was operated at the maximum amplitude and slew rate of 80 mT/m and 500 T/m/s, respectively. The geometric distortion correction was accomplished by iteratively determining up to the tenth order spherical harmonic coefficients using a fiducial phantom and position-tracking software, with seventh order correction utilized in the ACR test. Acoustic noise was measured with several standard clinical pulse sequences. The system passes all the ACR image quality tests. The acoustic noise as measured when the gradient coil was inserted into a whole-body MRI system conforms to the FDA NSR limits. The compact system simultaneously allows for high gradient amplitude and high slew rate. Geometric distortion concerns have been mitigated by extending the spherical harmonic correction to higher orders. Acoustic noise is within the FDA limits.

Fault Detection Circuit Based on IGBT Gate Signal

The detection circuit presented in this paper has the purpose of detecting short circuit and open circuit faults in insulated gate devices (IGBT). The detection circuit design is based on the analysis of the IGBT gate signal VGE, which is characterized by carrying out the fault detection within the IGBT switching times under test. The fast fault detection is due to the following considerations: a) Employing technology components with a high slew rate, allows the detection within the switching times, b) Employing fewer components allow the circuit design less expensive and faster, and This paper presents the experimental validation results for the proposed fault detection cases.

Universal Filter Design using 45nm CMOS-based DDCC for Bluetooth/ Zigbee Applications

limited performance of voltage mode Op-amps such as bandwidth, slew-rate etc. led the analog designer to search for other possibilities and other building blocks. Thus the current- mode active building blocks received considerable attention due to their larger dynamic range, high frequency, lower power consumption, high slew rate, better linearity, better accuracy and higher bandwidth. In this paper, a universal filter has been designed using Differential Difference Current Conveyor (DDCC) as an active building block. The filter provide low pass, high pass and band pass responses. The filter is also tuned for Zigbee and Bluetooth standards. The filter offers high bandwidth. The circuit implemented using DDCC provide non-interactive frequency control and employ only the grounded capacitors. The performance of the circuit is confirmed from HSPICE simulation results.

CFOA Based Band Pass and Band Stop Ladder Filter—A New Configuration

A new technique for the conversion of ladder based filter into CFOA based filter has been proposed. The technique uses signal flow graph and converts the existing LC ladder based filter into band pass & band stop configurations. The design of band pass and band stop filter has been realized using the proposed technique. The proposed configuration is implemented using CFOA as an active device and all the capacitors are grounded. CFOA based circuits have greater linearity, high dynamic rate, high slew rate and high signal bandwidth. Simulation has been carried out using simulation software P Spice (v10.1). The simulation results have been demonstrated and discussed.

A Compact Coupled Inductor for Interleaved Multiphase DC-DC Converters

A compact coupled inductor structure is proposed for interleaved multiphase synchronous buck converters used to power computer processors and memories that require high current and fast current slew rate. The new coupled-inductor structure reduces the winding resistor power loss and makes it possible to utilize ferrite magnetic material with low core loss. In this letter, several proposed converter implementations to achieve inverse inductor coupling are illustrated, and inductance and coupling coefficient variations are studied through a simplified reluctance model and Maxwell magnetic simulation. The inductor structure not only can be extended to multiple phases but also can be simplified to a single phase. The operation of the inductor is experimentally verified in a two-phase synchronous buck converter at switching frequency of 1 MHz.

응답 시간을 향상 시킨 외부 커패시터가 없는 Low-Dropout 레귤레이터 회로

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of at maximum load current 200mA.

Low Offset and High Slew Rate Buffer amplifier for LCD Application

The proposed buffer achieves low offset and high slew rate in proposed circuit NMOS folded cascode operation amplifier is used instead of rail to rail operation amplifier, use of only NMOS folded cascode operation amplifier reduces the number of MOS used in circuit and using auto zero negative feedback will provide full swing for positive and negative feedback polarity pixel, and to decrease the offset a current distributed load is used which increases DC gain of operational amplifier and as DC gain increases it reduces offset voltage and increases slew rate with same bias current used in folded and summing stage of operational amplifier. The proposed circuit is simulated and verified in LT-spice and Microwind simulation tool using 350nm CMOS TSMC foundry with 3.3 V supply voltage the offset calculated is around .2mV and slew rate is 14V/μs.

Feasibility of Imaging Tissue Electrical Conductivity by Switching Field Gradients with MRI.

Tissue conductivity is a biophysical marker of tissue structure and physiology. Present methods of measuring tissue conductivity are limited. Electrical impedance tomography and magnetic resonance electrical impedance tomography rely on passing an external current through the object being imaged, which prevents its use in most human imaging. More recently, tissue conductivity has been determined noninvasively from measurements of the radiofrequency (RF) field used in magnetic resonance imaging (MRI). This technique is promising, but conductivity at higher frequencies is less sensitive to tissue structure. Measuring tissue conductivity noninvasively at low frequencies remains elusive. It has been proposed that eddy currents generated during the rise and decay of gradient pulses could act as a current source to map low-frequency conductivity. This work centers on a gradient echo pulse sequence that uses large gradients before excitation to create eddy currents. The electric and magnetic fields during a gradient pulse are simulated by a finite-difference time-domain simulation. The sequence is also tested with a phantom and animal MRI scanner equipped with gradients of high gradient strengths and slew rates. The simulation demonstrates that eddy currents in materials with a conductivity similar to biological tissue decay with a half-life on the order of nanoseconds, and any eddy currents generated before excitation decay completely before influencing the RF signal. Gradient-induced eddy currents can influence phase accumulation after excitation, but the effect is too small to image. The animal scanner images show no measurable phase accumulation. Measuring low-frequency conductivity by gradient-induced eddy currents is presently unfeasible.

Design of a Low Voltage High Symmetrical Slew Rate Opamp Based on Self Cascode in UMC 0.18 <I>μ</I>m

Design of a Low Voltage High Symmetrical Slew Rate Opamp Based on Self Cascode in UMC 0.18 <I>μ</I>m

Analytical approximations for the rotating machine end-turn field distribution

The end turn grading of a form-wound machine is coupled capacitively to the stator conductor so that only derivatives of the conductor voltage are relevant to the performance of the end turn grading. In other words, the key factors are the “slew rate”, i.e., the derivative of the conductor voltage with respect to time, and the capacitance per unit length between the stator conductor and conductor armor tape (CAT) and nonlinear stress grading (SG). Both the CAT and SG can participate in grading for high slew rates, and a condition is provided for such participation. The peak field along the SG, and the decay thereof as a function of time after a transition, can be estimated from fundamental considerations.

Influence of fast rise voltage and pressure on partial discharges in liquid embedded power electronics

Initiation of partial discharges at the highly stressed regions of an Insulated Gate Bipolar Transistor (IGBT) can lead to degradation of the insulation and eventual total breakdown of the system. In this work, an experimental setup has been designed for the study of partial discharges (PDs) under different voltage waveforms. PD behavior of IGBT insulation was investigated using conventional and optical techniques. Influence of pressure and voltage wave shape is documented. The test environment was first characterized with point-plane geometry under sinusoidal and slow rise square voltage of up to 20 kVpeak and fast rise square voltage of up to +50 kV. The measured electrical and optical PDs showed good correlation, revealing that optical PDs can be relied on for the characterization of PD phenomena. High slew rate of the square voltage reduced the inception voltage and increased magnitude. The PD pattern from the trench shows the existence of space charges. The PDs which occurred within the triple point region are most likely attracted along the board interface and become surface discharges. Pressure suppresses the initiation and propagation of the discharge.

Two-Pole Integrator SQUID Readout Electronics With High Slew Rate and Small Closed-Loop Frequency Response Peak

Direct-readout electronics with high slew rate and small closed-loop frequency response peak is described by using a two-pole integrator for superconducting quantum interference device (SQUID) applications. In our experiment, a weakly damped niobium-SQUID magnetometer with a large flux-to-voltage transfer coefhcient ∂V/∂Φ of about 380 μV/Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> was used to suppress the contribution of direct-readout preampliher noise. A two-stage preampliher was employed, and integrator parameters were optimized to extend the system slew rate, while minimizing the closed-loop frequency response peak. A slew rate of 2.7 Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> /μs (at 10 kHz) is achieved with only 1-dB peak at 50 kHz in closed-loop frequency response, which means higher system stability. This system was verihed by recording undistorted transient electromagnetic held bipolar square-pulse signals, which required high slew rate and broad bandwidth.

Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

The conventional switched-capacitor amplifier faces design tradeoffs between settling accuracy and noise, in that high settling accuracy demands wide bandwidth but at the sacrifice of noise performance. In fact settling accuracy and noise exhibit different time dependence, which can be exploited to optimize the overall performance. Settling accuracy is determined by average bandwidth in the whole amplification phase, whereas the output noise of interest is determined by the bandwidth near the end of the phase. The proposed amplifier divides the amplification phase into two sub-phases. The first sub-phase starts with high bandwidth and high slew rate to approach the final value quickly. In the second sub-phase, the bandwidth can be significantly reduced, achieving the target settling accuracy but with much lower noise. This division allows the settling accuracy, noise, slew rate, and DC gain to be designed independently. A test chip is fabricated in a 65 nm CMOS process and operates at 90 MS/s. Measurements demonstrate that the proposed amplifier achieves 45% noise power reduction in the amplification phase along with improved linearity and lower power consumption, when compared with the conventional amplifier.

Controlled Load and Speed Transitions in a Multicylinder Recompression HCCI Engine

A model-based control strategy to track combustion phasing during load and speed transitions in the homogeneous charge compression ignition (HCCI) operating region of a multimode combustion engine is presented in this paper. HCCI transitions can traverse regions of high cyclic variability (CV), even if the steady state transition end points are stable with low CV. A control-oriented HCCI model for both the stable, low CV region and the oscillatory, high CV, late phasing region is used to design a controller that uses valve and fuel injection timings to track combustion phasing. Novel aspects of the controller include nonlinear model-inversion-based feedforward and gain scheduled feedback based on unburned fuel that reduces transient CV. Transitions tested on a multicylinder HCCI engine include load transitions at fixed engine speeds, simultaneous load, and speed transitions, and select FTP75 drive-cycle transitions with high load slew rates. Good combustion phasing tracking performance is demonstrated, and misfires are prevented.

Technologies for suppressing charge-traps in novel p-channel Field-MOSFET with thick gate oxide

High voltage laterally diffused MOS (LDMOS) FETs are widely used in analog applications. A Field-MOSFET with a thick gate oxide is one of the best ways of achieving a simpler design and smaller circuit footprint for high-voltage analog circuits. This paper focuses on an approach to improving the reliability of p-channel Field-MOSFETs. By introducing a fluorine implantation process and terminating fluorine at the LOCOS bird’s beak, the gate oxide breakdown voltage could be raised to 350 V at a high-slew rate and the negative bias temperature instability (NBTI) shift could be kept to within 15% over a product’s lifetime. By controlling the amount of charge in the insulating layer through improving the interlayer dielectric (ILD) deposition processes, a higher BVDSS of 370 V and 10-year tolerability of 300 V were obtained with an assisted reduced surface electric field (RESURF) effect. These techniques can supply an efficient solution for ensuring reliable high-performance applications.

High Junction Temperature and Low Parasitic Inductance Power Module Technology for Compact Power Conversion Systems

Advanced power module technology capable of taking advantage of the superior features of next-generation power devices, such as those fabricated with SiC and GaN, must be developed to create much more compact and cost-effective power conversion systems. New power modules based on such technology are especially required to allow fast switching of power devices in the extended junction temperature range. This paper describes the major technical challenges involved in sufficiently improving the thermal stress reliability of the critical package systems in SiC power modules and in markedly reducing internal parasitic inductance. Thermal stress reliabilities of the die attachment system, wire bonding system, and encapsulant system are successfully improved, all of which are shown to be able to achieve common life targets: 1) 3000 h for a storage test at 250 °C and 2) 3000 cycles for thermal cycling between −40 °C and 250 °C. A novel phase-leg power module capable of substantially reducing the loop inductance along the principal current tracks is proposed and fabricated by applying SiC-JFETs, SiC-Schottky barrier diodes, and the abovementioned reliable thermal stress package systems. Double pulse switching testing of the module reveals smaller drain-source voltage spikes and ringing even in turn-ON and turn-OFF transients at very high slew rates of current and voltage. Finally, a 0.34 L forced-air-cooled dc 600 V input ac 50 Hz 400 V 25 kW output three-phase SiC inverter is fabricated using three-phase leg modules and its operation is demonstrated at high-power levels.

Design and Implementation of High Gain, High Unity Gain Bandwidth, High Slew Rate and Low Power Dissipation CMOS Folded Cascode OTA for Wide Band Applications

A novel differential input pair and single output OTA is designed in this paper. This FCOTA is designed by using current mirror and its enhanced gain parameter and also is reduce the power dissipation and increase the gain bandwidth. Simulation results are performed using Mentor Graphics software model for CMOS TSMC 180 nm process technology. The supply voltage is given 1.8 v. The designed FCOTA has different capacitive load and according its Gain, Unity Gain Bandwidth, Power Dissipation, Phase Margin and Slew Rate are measured. Gain, Unity Gain Bandwidth and Slew Rate are optimizing up to 97.37 db, 20.83 GHz and 3.5075 KV/μs respectively. The power dissipation reduces up to 8.31 μW. This FCOTA is designed for wide band application because of high gain and high bandwidth and low power dissipation.

Dual output Rail to Rail CMOS Buffer Amplifier with Low Power and High Slew Rate for LCD Source Driver IC

Dual output Rail to Rail CMOS Buffer Amplifier with Low Power and High Slew Rate for LCD Source Driver IC