High Resolution SAR ADCs Research Articles

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380–16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 μW while operating at sampling frequency of 500 MS s–1 at supply voltage of 1 V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs

The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs

A low‐cost digital calibration scheme for high‐resolution SAR ADC using Adaptive‐LMS

This paper presents a novel low-cost digital calibration scheme using Adaptive-LMS for high-resolution SAR ADCs. This proposed Adaptive-LMS is realized by perturbing adaptive analog offset and skipping several LSBs' calibration. Compared with a digital calibration scheme based on conventional LMS, the design saves not only die cost but also testing cost (less testing time). During the testing process, the proposed method requires only 16,000 samples to calibrate the capacitor mismatch and the SNDR is improved from 54.1 dB to 68.1 dB for a 12-bit SAR ADC.

Voltage Comparator With 60% Faster Speed by Using Charge Pump

This brief proposes a novel comparator to greatly increase its comparison speed while not degrading its noise performance. This comparator is well suited for high-speed high-resolution SAR ADCs. Its structure is based on the classic Miyahara’s two-stage comparator with the addition of only an extra charge pump. This simple modification greatly accelerates both the second-stage amplification phase and the regeneration phase, leading to significantly increased comparison speed. Meanwhile, the noise performance is not degraded, because the input pair transconductance of the second stage is increased while its integration time is decreased. For fair comparison, both the proposed comparator and the classic Miyahara’s comparator are implemented in the same 40nm CMOS process. Measurement results show that the proposed comparator speed is faster by 60% compared with the classic Miyahara’s comparator, while the input-referred noise is similar.

Design of Power Efficient Dynamic Latch Comparator for High Resolution SAR ADCs

Design of Power Efficient Dynamic Latch Comparator for High Resolution SAR ADCs

Analyses of parasitic capacitance effects and flicker noise of the DAC capacitor array for high resolution SAR ADCs

This paper analyses the effects of parasitic capacitances of unit capacitors on the accuracy and the noise performance of the DAC capacitor array in a SAR ADC, showing that thermal noise of the array decreases while gain error is introduced. The gain error is almost independent of the number of bits, but the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance analysis of a 10-bit poly-poly array shows a large difference between the top-plate and bottom-plate parasitic capacitances so that the gain error can be decreased by 152 times when top-plates are connected together as the output node of the array. The switching transistors' flicker noise calculation for a 10-bit and an 18-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, but should be considered for the higher resolution SAR ADCs.

Analyses of parasitic capacitance effects and flicker noise of the DAC capacitor array for high resolution SAR ADCs

This paper analyses the effects of parasitic capacitances of unit capacitors on the accuracy and the noise performance of the DAC capacitor array in a SAR ADC, showing that thermal noise of the array decreases while gain error is introduced. The gain error is almost independent of the number of bits, but the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance analysis of a 10-bit poly-poly array shows a large difference between the top-plate and bottom-plate parasitic capacitances so that the gain error can be decreased by 152 times when top-plates are connected together as the output node of the array. The switching transistors' flicker noise calculation for a 10-bit and an 18-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, but should be considered for the higher resolution SAR ADCs.

Self-Dithering Technique for High-Resolution SAR ADC Design

In this brief, a high-resolution successive-approximation-register analog-to-digital-conversion architecture for biomedical data acquisition is proposed. A filtered least-significant-bit segment is employed as a dither to improve the resolution. Theoretical analysis and behavioral simulations show that the error of a most-significant-bit segment can be converted into shaped noise if the input signal is sufficiently small. The proposed self-dithering technique can be used, together with averaging, to improve the signal-to-noise ratio and the differential nonlinearity (DNL) performance. The performance improvement is similar to that of a conventional nonsubtractive scheme using a uniform deterministic dither but with simplified hardware and reduced computation complexity.

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300MS/s, it consumes 1.27mW and achieves an SNDR of 60dB, an SFDR of 67.5dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380μm2.

A Novel Two-Split Capacitor Array with Linearity Analysis for High-Resolution SAR ADCs

A Novel Two-Split Capacitor Array with Linearity Analysis for High-Resolution SAR ADCs

Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successive-approximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.

Novel hybrid D/A structures for high-resolution SAR ADCs—analysis, modeling and realization

An intermittent-sleeping C–R hybrid D/A structure, a resistor-reusing R–C hybrid D/A structure and an R–C–R combined D/A structure are researched with theoretical analysis and Matlab modeling in this paper. The switching power and passive components' matching requirement of these D/A structures are discussed in detail. Three SAR ADCs with these three novel structures are realized based on SMIC 0.18μm CMOS, SMIC 90nm CMOS and UMC 90nm CMOS, respectively. The theoretical analysis, modeling verification and circuit realization proves the applicability of these three D/A conversion networks to high-resolution SAR ADCs.

D/A conversion networks for high-resolution SAR A/D converters

An intermittent-sleeping C-R hybrid structure and a resistor-reusing R-C hybrid structure are presented for high-resolution SAR A/D converters. The switching power of these conversion networks and the matching requirements of their internal passive components are researched based on high-level Matlab modelling. Their applicability to high-resolution SAR ADCs is proven by realisation of two SAR A/D converters with these two novel D/A networks.