High-resolution Analog-to-digital Converters Research Articles

Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC.

An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio.

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter's sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively.

High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. The majority of the dynamic comparators can only operate at high speeds when the input difference voltage is large enough. Due to the limited pre-amplifier gain, the comparators’ performance deteriorates at lower input difference voltages, which is not suitable for high-speed, high-resolution ADCs. A double-tail dynamic comparator with a pair of auxiliary inverters is proposed to alleviate this problem. With the proposed comparator, the pre-amplifier’s differential gain is increased, and the latch regeneration time is reduced by the auxiliary inverter pair resulting in faster comparison operations. The proposed comparator is designed, simulated, and compared with the latest topologies in 65 nm CMOS technology. The performance metrics such as delay, kickback noise, energy consumption per bit, rms noise, and power delay product are evaluated and compared with the state-of-the-art architectures. The proposed technique can be applied to any dynamic comparator that has differential signals at the output of the pre-amplifier stage. Simulations show that the auxiliary inverter pair improves the comparator’s speed by more than 10%.

A 1-bit DACs precoding for MU-MIMO based on binary equilibrium constraint: An alternating direction method

High power consumption is one of the main problems in the practical application of massive multi-user multi-input-multi-output (MU-MIMO) systems, and using 1-bit digital-to-analog converters (DACs) instead of high-resolution DACs is an effective way to reduce the power consumption of massive MU-MIMO systems. How to design efficient precoding schemes to improve the performance of 1-bit MU-MIMO systems has become a hot research field. This paper mainly studies the precoding problem of 1-bit DACs based on minimum mean squared error (MMSE). We first transform the non-convex constraints of the traditional optimization problem using binary equilibrium constraints. Then, to solve the transformed objective problem, we establish a framework based on the alternating direction method (ADM), use the fast projection gradient (FPG) method, and propose an alternating maximum minimum (AMM) algorithm to solve the optimization variables alternately. We have verified the convergence of the proposed algorithm and analyzed the accuracy of the proposed ADM framework and the computational complexity of the proposed algorithm in detail. In the simulation section, we analyze the uncoded bit error rate (BER) performance of the proposed algorithm in phase-shift keying (PSK) modulation and quadrature amplitude modulation (QAM) modes. The simulation results show that compared with existing advanced algorithms, the proposed algorithm can achieve performance advantages of about 1 dB and 2 dB in QPSK modulation mode and 16QAM modulation mode, respectively.

Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS

Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparators’ performance degrades at small input difference voltages due to a limited preamplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is proposed. The comparator improves the differential gain of the preamplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in a 65 nm CMOS technology. The results show that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V.

Performance analysis of massive MIMO systems with low-resolution ADCs and IQI

In massive multiple-input multiple-output (MIMO) systems, the substantial increase in the number of antennas leads to a surge in hardware cost and power consumption. Meanwhile, the impact of IQ imbalance (IQI) on system performance also tends to be serious. In this paper, closed-form expressions for the achievable rates of maximum-ratio combining (MRC) receivers are derived for uplink massive MIMO systems with both low-resolution analog-to-digital converters (ADCs) and IQI. Based on the derived closed-form expression, the influence of system parameters on the achievable rate is analyzed. The simulation results verify the accuracy of the theoretical results. It is found that low-resolution ADC and IQI will degrade the achievable rate compared with employing high resolution ADCs, but this loss can be compensated for by increasing the number of base station (BS) antennas, so as to significantly increase the energy efficiency.

An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory

This letter proposes a bidirectional long-short-time-memory (bi-LSTM)-based analog-to-digital converter (ADC) background calibration method with a clock jitter compensation function. Different from traditional calibration algorithms, the proposed algorithm utilizes the sequence property of the signal by introducing an LSTM network. The network contains three parts, including a linear layer for input encoding, a refine layer for sequence processing, and a linear layer for output decoding. Two ADCs are used to train the network, one of which is the target to be calibrated, that is, a high-speed high-resolution ADC, and the other is a low-speed ultra-high-resolution ADC producing the ideal signal. After the training stage, the network can be used as a postprocessor for the target ADC to compensate for the systemic errors and clock jitter, simultaneously. In the experiments, the proposed method is used to calibrate an ADC12D1600RFIUT, realizing the improvement of signal-to-noise distortion ratio (SNDR) from 43.41 to 66.82 dB and SFDR from 56.95 to 98.93 dB.

Transmit Code and Receive Filter Design for PMCW Radars in the Presence of One-Bit ADC

Phase-modulated continuous-wave (PMCW) radar is an emerging technology in various civilian applications. Due to the high bandwidth of the PMCW signal, it needs high-speed analog-to-digital converters (ADCs). High-resolution ADCs supporting this high bandwidth are expensive, have a big size on the chip, and consume high power, which are significant challenges for radar. A solution to deal with the aforementioned challenges is to use low-resolution, or in the most extreme case, one-bit ADCs. In this article, we aim at designing the transmit code and the receive filter for the PMCW radar in the presence of one-bit ADC at the receiver side. To this end, we introduce the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mean</i> integrated sidelobe level metric, called MISL. MISL generalizes the well-known ISL metric for nonideal ADC usage at the receiver side and takes the effect of noise and target backscattering coefficient into account. For mathematical tractability, we employ the maximum likelihood estimation of the target backscattering coefficient. This leads to casting an optimization problem that does not need knowledge about noise and target characteristics. We utilize the cyclic optimization procedure to optimize the transmit code and the receive filter. The filter design subproblem admits a closed-form solution, whereas we obtain a solution to transmit code design subproblem via the coordinate descent framework. Numerical examples illustrate the superior performance of the proposed method compared to benchmarks that design sequences assuming ideal ADC at the receiver.

Deep Learning-Based Channel Estimation for mmWave Massive MIMO Systems in Mixed-ADC Architecture.

Millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems can significantly reduce the number of radio frequency (RF) chains by using lens antenna arrays, because it is usually the case that the number of RF chains is often much smaller than the number of antennas, so channel estimation becomes very challenging in practical wireless communication. In this paper, we investigated channel estimation for mmWave massive MIMO system with lens antenna array, in which we use a mixed (low/high) resolution analog-to-digital converter (ADC) architecture to trade-off the power consumption and performance of the system. Specifically, most antennas are equipped with low-resolution ADC and the rest of the antennas use high-resolution ADC. By utilizing the sparsity of the mmWave channel, the beamspace channel estimation can be expressed as a sparse signal recovery problem, and the channel can be recovered by the algorithm based on compressed sensing. We compare the traditional channel estimation scheme with the deep learning channel-estimation scheme, which has a better advantage, such as that the estimation scheme based on deep neural network is significantly better than the traditional channel-estimation algorithm.

A 12-b Subranging SAR ADC Using Detect-and-Skip Switching and Mismatch Calibration for Biopotential Sensing Applications.

This paper presents a 12-b successive approximation register (SAR) analog-to-digital converter (ADC) for biopotential sensing applications. To reduce the digital-to-analog converter (DAC) switching energy of the high-resolution ADC, we combine merged-capacitor-switching (MCS) and detect-and-skip (DAS) methods, successfully embedded in the subranging structure. The proposed method saves 96.7% of switching energy compared to the conventional method. Without an extra burden on the realization of the calibration circuit, we achieve mismatch calibration by reusing the on-chip DAC. The mismatch data are processed in the digital domain to compensate for the nonlinearity caused by the DAC mismatch. The ADC is realized using a 0.18 μm CMOS process with a core area of 0.7 mm2. At the sampling rate fS = 9 kS/s, the ADC achieves a signal-to-noise ratio and distortion (SINAD) of 67.4 dB. The proposed calibration technique improves the spurious-free dynamic range (SFDR) by 7.2 dB, resulting in 73.5 dB. At an increased fS = 200 kS/s, the ADC achieves a SINAD of 65.9 dB and an SFDR of 68.8 dB with a figure-of-merit (FoM) of 13.2 fJ/conversion-step.

MIMO Networks With One-Bit ADCs: Receiver Design and Communication Strategies

High resolution analog to digital converters (ADCs) are conventionally used at the receiver terminals to store an accurate digital representation of the received signal, thereby allowing for reliable decoding of transmitted messages. However, in a wide range of applications, such as communication over millimeter wave and massive multiple-input multiple-output (MIMO) systems, the use of high resolution ADCs is not feasible due to power budget limitations. In the conventional fully digital receiver design, where each receiver antenna is connected to a distinct ADC, reducing the ADC resolution leads to performance loss in terms of achievable rates. One proposed method to mitigate the rate-loss is to use analog linear combiners leading to design of hybrid receivers. Here, the hybrid framework is augmented by the addition of delay elements to allow for temporal analog processing. Two new classes of receivers consisting of delay elements, analog linear combiners, and one-bit ADCs are proposed. The fundamental limits of communication in single and multi-user (uplink and downlink) MIMO systems employing the proposed receivers are investigated. In the high signal to noise ratio regime, it is shown that the proposed receivers achieve the maximum achievable rates among all receivers with the same number of one-bit ADCs.

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

This paper presents a calibration-free, 16-channel, 14-bit, 50-MS/s, pipelined successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) for ultrasound imaging systems. A reference sharing scheme with reduced buffers is proposed to improve area-and-power efficiency, which is essential for multi-channel systems. Based on this, a three-stage, pipelined-SAR ADC architecture with reference/op-amp sharing and optimized stage resolution distribution is proposed. The prototype ADC is designed in a 0.18-μm process with peripheral circuits integrated, including low-voltage differential signaling (LVDS), bandgap, etc. It achieves a robust and calibration-free performance with 68.25-dB signal to noise and distortion ratio (SNDR) and 82.19-dB spurious-free dynamic range (SFDR), translating into a competitive figure of merit (FoM) of 0.47 pJ/conversion-step among other high-resolution ADCs used in ultrasound applications.

The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing

In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips and multiplexers to generate high-resolution high-speed signals that can be used for testing high-resolution ADC chips based on the principle of time-alternating sampling. This article explains its method, analyzes its error and proposes a digital pre-processing method to reduce the error. Finally, the actual circuit is designed, and the method is verified on the circuit. The test results prove the effectiveness of this method for generating high-resolution ADC test signals.

Channel Estimation in MIMO Systems With One-Bit Spatial Sigma-Delta ADCs

This paper focuses on channel estimation in single-user and multi-user MIMO systems with multi-antenna base stations equipped with 1-bit spatial sigma-delta analog-to-digital converters (ADCs). A careful selection of the quantization voltage level and phase shift used in the feedback loop of 1-bit sigma-delta ADCs is critical to improve its effective resolution. We first develop a quantization noise model for 1-bit spatial sigma-delta ADCs. Using the developed noise model, we then present a two-step channel estimation algorithm to estimate a multipath channel parameterized by the gains, angles of arrival (AoAs), and angles of departure (AoDs). Specifically, in the first step, the AoAs are estimated using uplink pilots, which excite all the angles uniformly. Next, in the second step, the AoDs are estimated by progressively refining uplink beams through a recursive bisection procedure followed by a weighted least squares path gain estimator. For this algorithm, we propose a technique to select the quantization voltage level and phase shift. Through numerical simulations, we demonstrate that with the proposed parametric channel estimation algorithm, MIMO systems with 1-bit spatial sigma-delta ADCs perform significantly better than those with regular 1-bit ADCs and are on par with MIMO systems having high-resolution ADCs

A Folding Approach for Multiple Antenna Arrays Using Low-Resolution ADCs

Both massive multiple-input multiple-output (MIMO) and millimeter wave (mmWave) systems are receiving much attention for 5G and beyond-5G wireless access. When using a large antenna array, there are numerous challenges in designing low-power and cost-effective hardware. Most notably, the traditional approach of using high-resolution analog-to-digital converters (ADCs) at each element leads to both costly and high-power consumption devices. This has motivated research on multiple antenna arrays that use a low-resolution ADC at each element. We present a new framework for designing a multiple antenna array using a low-resolution ADC at each element, with the low-resolution ADC composed of simple shift and modulo analog processing and a sign quantizer. This modulo technique, called folding, has previously been utilized in the design of high-speed high-resolution ADCs. Using theory from folded ADCs, we show how to jointly design the modulo processing used across the elements. We show that our framework can provide substantial rate improvements including providing a linear growth in rate with the number of antennas at high SNR, as opposed to the logarithmic growth with the number of antennas provided by a sign-based low-resolution ADC array. We also explore how antenna ordering strategies can be used. We utilize Monte Carlo simulations to back our analysis.

Algorithms for accurate spectrum measurement of high-resolution analog-to-digital converter with non-coherent sampling.

In Analog-to-Digital Converter (ADC) spectrum measurement, the realization of coherent sampling is difficult to implement, which has always been one of the bottlenecks. When coherent sampling is not available, researchers have been looking for some precise methods to test high-resolution ADCs under non-coherent sampling conditions. This study introduces two algorithms to, respectively, resolve harmonic distortion and ADC amplitude clipping problems with non-coherent sampling based on the idea of replacement. In algorithm 1, in order to accurately depict a signal spectrogram with harmonics under non-coherent sampling, signal fundamental and harmonics are basically estimated twice, a rough estimate and a fine estimate to get accurate values, and then they are replaced by a coherent sampling spectrum. In algorithm 2, we first determine the sampling period, then propose a three-parameter approach to calculate parameters of clipped signal, analyze and correct the parameter error, and finally apply the corresponding idea signal to replace the clipped signal. This paper proves the two algorithms' superiority through a lot of simulation results, such as 12-bit, 14-bit, and 16-bit ADC tests. Finally, we process the experiment on the ADC chip automatic test system to obtain 16-bit AD9268 spectrum data and verify the effectiveness of the two algorithms. The two algorithms correct the spectrum error caused by non-coherent sampling and clipping, ideally suitable for high-resolution ADCs.

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping

Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power from a 1.1-V supply and occupies 0.061 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

Joint Detection and Decoding of Mixed-ADC Large-Scale MIMO Communication Systems With Protograph LDPC Codes

Nowadays, large-scale multiple-input multiple-output (LS-MIMO) with low-resolution analog-to-digital converters (ADCs) is a favorable transmission scheme for 5G and beyond wireless networks to reduce the power consumption of the radio frequency chains and to increase the network capacity. This paper derives the joint message-passing detection and decoding algorithm based on the double-layer graph for LS-MIMO communication systems with mixed-ADCs. The new protograph extrinsic information chart (PEXIT) algorithm is developed to analytically evaluate the performance of protograph low-density parity-check code under various mixed-ADC combinations and LS-MIMO configuration scenarios. The simulation results validate the accuracy of the proposed algorithm. Furthermore, our experiments show that the mixed-ADC system can achieve a significant power gain even when only one received antenna is equipped with high-resolution ADCs. It is observed that 4-bit or 5-bit resolution is an optimal choice for the high-resolution receive antennas. Interestingly, mixed-ADC systems with Ternay-ADCs generally provide significant gains at the cost of the increase in the average resolution by a fraction of a bit. There are specific scenarios where the Ternary-ADC-based system outperforms the 1-bit-ADC based system at the same or lower average resolution. In the particular case of 16 ×16 MIMO configuration where the number of low-resolution antennas is N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> = 12 and the number of high-resolution antennas is N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> = 4, the Ternary-ADC based system can obtain a power gain of about 2 dB at the frame error rate (FER) or bit error rate (BER) level of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> .